Abstract: An embodiment of the present invention is electronic circuitry for producing an I-phase quadrant pointer (FI) and a Q-phase quadrant pointer (FQ) by sampling a feed clock (IC) and a quadrature feed clock (QC), the circuitry comprises: a first quadrant detector (406, FIG. 5) for producing the Q-phase quadrant pointer in response to receipt of the feed clock and input data; a second quadrant detector (408, FIG. 5) for producing the I-phase quadrant pointer in response to receipt of the feed clock and the input data; and wherein the I-phase quadrant pointer and the Q-phase quadrant pointer can be utilized to determine the phase quadrant of the input data.

Abstract: A sensor (210) for diagnosis and prognosis of semiconductor device fabrication processes measures specular, scattered, and total surface reflectances and transmittances of semiconductor wafers (124). The sensor (210) includes a sensor arm (212) and an opto-electronic control box (214), for directing coherent electromagnetic or optical energy in the direction of semiconductor wafer (124). Opto-electronic control box (214) includes circuitry for measuring the amounts of laser powers coherently reflected from and transmitted through the semiconductor wafer (124) surface and the amounts of electromagnetic powers scatter reflected from and transmitted through the semiconductor wafer (124) surface. Specular, scattered, and total reflectance and transmittance as well as surface roughness values for semiconductor wafer (124) are determined based on measurements of coherent and scatter reflected and transmitted laser powers.

Abstract: One embodiment of the present invention is a battery (17) (preferably configured in the form of a wrist band, headband, necklace, arm band or a waist band) for a personal electronic device (preferably a watch, a personal communications device, a personal television, or a personal radio), the battery located external to the personal electronic device and comprising: an outer surface (12); an anode (28); a cathode (30); and a connector (10) to electrically connect the battery to the personal electronic device. The battery of the present invention can be flexible. In addition the battery may further include a plurality of photovoltaic cells (22) disposed on the outer surface of the battery, whereby the battery and the photovoltaic cells are operable to supply power to the personal electronic device. Additionally, the plurality of photovoltaic cells would be operable to charge the battery during periods other than when the battery is supplying power to the personal electronic device.

Abstract: A digital circuit (11) for compelling storage of attributes and for providing output signals indicating status of the storage of attributes, the digital circuit comprising: a digital storage device (26); a first combinational logic circuit (20) connected to the digital storage device (26) for enabling the digital storage device (26) to store the attributes based upon a set of stable first compelled inputs and an enable signal; a second combinational logic circuit (18) connected to the digital storage device for clearing the digital storage device (26) based upon a set of stable second compelled inputs and a clear signal; a first logic gate (30) connected to the digital storage device (26) and the first combinational logic circuit (20) for outputting a signal representative of the attribute being stored in the digital storage device (26); and a second logic gate (28) connected to the digital storage device (26) and the second combinational logic circuit (18) for outputting a signal representative of the digita

Abstract: An RF identification system having an interrogator operable to send RF interrogations to a transponder and to receive RF responses from the transponder. The interrogator is in electrical communication with a closed slot antenna. The closed slot antenna is formed by an an outer visual magnetic loop and an inner visual magnetic loop such that the antenna has a superior magnetic field when compared to a balanced double loop antenna with an equal area and a superior far-field noise suppression when compared to the single loop antenna. The antenna receives said RF responses from the transponder and provides said RF responses to said interrogator. Other devices, systems and methods are also disclosed.

Abstract: A system (10) for run-to-run control of semiconductor wafer processing is provided. An input/output device (12) receives a desired quality characteristic for a particular semiconductor fabrication process. A generating circuit (22) uses a model to generate appropriate process parameters for a processing unit (20) and an expected quality characteristic. An adjusting circuit (16) functions to adjust process parameter inputs of the processing unit (20). In-situ sensor (18) functions to measure a quality characteristic of the process in the processing unit (20) on a real-time basis. A comparing circuit (24) functions to compare the measured quality characteristic with the expected quality characteristic. A model adjusting circuit (26) may adjust the model of the generating circuit (22) if the measured quality characteristic varies from the expected quality characteristic by more than a predetermined statistical amount.

Abstract: An embodiment of the instant invention is a system for displaying information related to the performance of an automobile, the system comprising: a power supply; a display means, the display means includes gauges; a plurality of sensors for providing data; and a microcontroller for receiving the data from the plurality of sensors and for driving the display means based on receipt of the data from the plurality of sensors, the microcontroller fabricated on a singular semiconductor chip and comprising: a voltage regulator, the voltage regulator comprising high power transistors; a gauge driver for driving the display means, the gauge driver comprising high power transistors; a program memory array for storing program instructions; and a random access memory array for storing the data provided by the plurality of sensors.

Abstract: This antifuse includes: a sublithographic conductive pattern (18); an antifuse material (24) overlying said sublithographic conductive pattern (18); and a conductive layer (26) overlying the antifuse material (24) to form a reduced area antifuse (10). Other devices, systems and methods are also disclosed.

Abstract: A protection device, circuit, and a method of forming the same. A field oxide drain extended nMOS (FODENMOS) transistor (10) is located in an epitaxial region (16). The FODENMOS transistor (10) comprises a field oxide region (36a) that extends from the source diffused regions (22) to over a portion of the extended drain region (20). A drain diffused region (24) is located within the extended drain region (20). A gate electrode (40) may be located above the field oxide region (36a) if desired. Accordingly, there is no thin oxide interface between the gate electrode (40) and the extended drain region (20) that can lead to low ESD protection.

Abstract: A method for obtaining real-time emissivity and temperature values of a semiconductor wafer in a processing system having at least one lamp (preferably a plurality of lamps arranged in a plurality of zones so as to provide multizone temperature and emissivity values for the semiconductor wafer) arranged in at least one zone, the method using a reference wafer having a known reflectivity and the method comprising the steps of: measuring pyrometry signals for the reference wafer (step 202) and generating calibration curves from the measurements; measuring pyrometry signals for the semiconductor wafer; and obtaining the temperature and emissivity values (step 222) from the calibration curves and the measured pyrometry signals (step 220) for the semiconductor wafer.

Abstract: One embodiment of the present invention is a method of simultaneously forming high-voltage (12) and low-voltage (10) devices on a single substrate (14), the method comprising: forming a thin oxide layer (18) on the substrate, the thin oxide layer having a desired thickness for a gate oxide for the low-voltage device; selectively forming a gate structure (30) for the high-voltage device, the thin oxide is situated between the gate structure and the substrate; and selectively thickening the thin oxide under the gate structure while keeping the thin oxide layer utilized for the low-voltage device at the desired thickness.

Abstract: A method and apparatus are disclosed for safely suspending and resuming operation of an electronic device. The method comprises the step of generating a DUT-NXCLK-IN in response to a first NXCLK-IN to drive an electronic device 12 DUT-CLK-OUT is received from the device 12 wherein DUT-CLK-OUT comprises DUT-NXCLK-IN divided by a first value. ESYNER-CLK-OUT is generated by dividing NXCLK-IN by the first value. ESYNER-CLK-OUT is synchronized to signal-DUT-CLK-OUT. DUT-NXCLK-IN is disabled in response to a test grant signal TEST-GRANT when the ESYNER-CLK-OUT is in a predetermined one of a plurality of states. The disabled DUT-NXCLK-IN is re-enabled in response to the test grant signal TEST-GRANT when ESYNER-CLK-OUT is in the state immediately following the predetermined one of a plurality of states.

Abstract: An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

Abstract: An elevated source/drain structure is described in which the channel region is thinned by local oxidation and wet etch while the source/drain region remained thick. This structure achieves source/drain resistances as small as 300 ohm-.mu.m for NMOS, which makes possible high drive currents in deep submicron thin-film SOI/MOSFET.

Abstract: Local reference voltage sub-circuits for ECL circuits are provided. The sub-circuits operate by a principal based on gating a current mirror. The sub-circuits described are superior to conventional approaches because less current is required during switching, better transfer characteristics are obtained and there exists, in some cases, less susceptibility to latch-up in comparison with conventional approaches.

Abstract: The invention discloses modifying the surface of a device to reduce transition region growth so that higher anneal temperatures can be used with the device to optimize dielectric quality, reduce defect density, and achieve the lowest possible dielectric leakage. One method of surface modification occurs when an impurity such as germanium is added to a silicon surface before deposition of TA 205 to serve as a diffusion barrier or retardant, which would inhibit the growth of the silicon TA205 transition region at higher temperatures and prevent capacitance degradation. Germanium is a good choice for this application because of its similarities to silicon. However, other materials can also serve as barriers.

Abstract: A delay circuit (10) for a memory device introduces asymmetrical delay to prevent a false write operation from being performed by the memory device, The asymmetrical delay can be disabled during read operations in response to a control signal (CS) in order to allow for fast column access.

Abstract: The parallel antifuse scheme may be applied to a field programmable gate array architecture (10) having a logic module (16) with an output coupled to an output track (34, 54, 114, 144, 178, 198) coupled via a cross antifuse (38, 58, 116, 184, 208) to an connecting track (36, 56, 64, 118, 154, 182, 205, 206). The connecting track is further coupled via at least one cross antifuse (44, 46, 72, 74, 120, 122, 160, 162, 190, 218, 220) to at least one input track (40, 42, 68, 70, 188, 214, 216) coupled to an input of at least one logic module. The circuit includes a compensation track (124, 150, 180, 200) running generally in parallel with the output track and at least one parallel antifuse (125, 158, 186, 212) programmably coupling the compensation track (124, 150, 180, 200) and the connecting track. One or more controllable switch (130, 152, 174, 176, 194, 196), such as a pass transistor, is coupled between the output track and the compensation track.

Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is operable to receive at least one word of data from data memory 20 and test the word against a preselected search test condition. Control circuitry 24 is operable in response to control instructions received from the broadcast memory 22 to control the transfer of the word of data from the data memory 20 to the search circuitry 26, 52 and the test of the word by the search circuitry 26, 52.

Abstract: An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data and computational results. A broadcast memory 22 includes rows and columns of storage locations for holding control instructions. Computing circuitry 26 is provided which is operable to perform a first computational operation using first and second words of data retrieved from the data memory 20 and perform a second computational operation using a result from the first operation and a result from a previous operation. Control circuitry 24 is operable in response to control instructions received from broadcast memory 22 to control the transfer of the first and second words of data from the data memory 20 to said computing circuitry 26 and the performance of the first and second operations.