Abstract: In an embodiment of the present invention is electronic circuitry for producing a clock signal, and its quadrature, whose phase matches the phase of input data in response to receipt of the input data and a reference clock signal, the circuitry comprises: circuitry for providing the quadrature of the reference clock signal; circuitry for providing a Q-phase quadrant pointer in response to the input data, and the reference clock; circuitry for providing an I-phase quadrant pointer in response to the input data, and the quadrature reference clock; circuitry for providing a phase signal in response to the produced clock, the quadrature of the produced clock and the input data; circuitry for providing a phase-change signal for specifying whether to rotate the phase of the produced clock signal in one direction or the other, the circuitry operable in response to the I-phase quadrant pointer, Q-phase quadrant pointer and the produced clock signal; a first phase rotator for changing the phase of the produced clock i

Abstract: A computer controlled system for real-time control of semiconductor wafer fabrication process uses a multi-point, real-time, non-invasive, in-situ pyrometry-based temperature sensor with emissivity compensation to produce semiconductor wafer reflectance, transmittance, and radiant heat energy measurements. The temperature values that the sensor determines are true temperatures for various points on the wafer. The process control computer stores surface roughness values for the semiconductor wafer being examined. The surface roughness values are produced by surface roughness sensor that makes non-invasive and in-situ measurements. The surface roughness sensor performs roughness measurements of the semiconductor wafer based on coherent reflectance and scatter reflectance of the wafer. Based on surface roughness measurements, the process control computer can use the real-time, in-situ measurements of the multi-point pyrometry-based sensor to obtain real-time measurements of time wafer temperature distribution.

Abstract: A method and system form a globally planar material layer (44) on a semiconductor wafer (32). The method and system consist of a chuck (58) and a chiller (56) to cool down semiconductor wafer (32) to a predetermined temperature in order to condense multiple liquid film layers (38, 40, 42) to produce a globally planar material layer (44) from a suitable condensable process vapor. At least one process energy source (72 and 74) reactively solidifies the liquid films on the semiconductor wafer (32) and may include a remote plasma source, a radio-frequency plasma source, or a photon source. The steps and apparatus for condensing and solidifying the material layer form a progressive globally planar layer on the semiconductor wafer surface.

Abstract: An integrated process is shown for the fabrication of one or more of the following devices: (n-) and (p-) channel low-voltage field-effect logic transistors (556/403); (n-) and (p-) channel high-voltage insulated-gate field-effect transistors (557, 405) for the gating of an EEPROM memory array or the like; a Fowler-Nordheim tunneling EEPROM cell (558); (n-) and (p-) channel drain-extended insulated-gate field-effect transistors (407, 560); vertical and lateral annular DMOS transistors (409, 561); a Schottky diode (411); and a FAMOS EPROM cell (562). A "non-stack" double-level poly EEPROM cell (676) with enhanced reliability (676) is also disclosed.

Abstract: A preferred embodiment of the present invention is a method of forming a device on a semiconductor substrate of a first conductivity type, the method comprising: forming a semiconducting layer on the substrate; etching alignment marks in the semiconducting layer (102); forming a first mask on the semiconducting layer to expose portions of the semiconducting layer; introducing dopants of a second conductivity type opposite the first conductivity type into the exposed portions of the semiconducting layer to form high-voltage tanks (104); removing the first mask; annealing the dopants introduced to form high-voltage tanks of a second conductivity type (105); forming a second mask on the semiconducting layer to expose second portions of the semiconducting layer; introducing dopants of a second conductivity type into the exposed second portions of the semiconducting layer to form low-voltage tanks (106); removing the second mask; forming a third mask on the semiconducting layer to expose third portions of the semi

Abstract: An embodiment of the present invention is a digital circuit (block 12 of FIG.

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions (103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: An integrated circuit capacitor has a semiconductor die and a plurality of field effect transistors fabricated on the die and having gates, sources and drains. The gates are connected to each other as one side of the capacitor. The sources and drains are connected together as another side of the capacitor. A color palette has a die with circuitry including a dot clock buffer with transistors connected to supply rails and the integrated circuit capacitor having a plurality of the parallel-connected field effect transistors connected across the supply rails. The dot clock buffer has an output distributed directly to the rest of the circuitry. Other capacitors, buffers, systems and methods are also disclosed.

Abstract: A current duplicator (10) is provided for receiving a calibration current and providing an output current to a load (10). Current duplicator (10) includes a transconductor (14) having a differentially coupled input with a parasitic capacitance for storing a differential voltage during a supply period. This parasitic capacitance also converts a difference current into the voltage during a feedback period. The difference current is equal to the difference between the output current and the calibration current. Transconductor (14) converts the voltage into the output current. The current duplicator also includes a first switch network for coupling the output current to the load (12) during the supply period. The output current remains within a predetermined amount from the calibration current during the supply period. A second switch network feeds back the difference current to the input during the feedback period at least until the output current becomes substantially equal to the calibration current.

Abstract: An embodiment of the present invention relates to a semiconductor wafer structure, the wafer structure comprising: a semiconductor substrate; a plurality of temperature sensing elements (12) disposed over the semiconductor substrate, where temperature sensing elements (12) are fabricated so that an electrical characteristic of the temperature sensing element changes as the temperature of the wafer changes; and a plurality of interconnection lines (10, 14) connecting the temperature sensing elements (12) to external devices. In addition the semiconductor wafer structure includes a passivation layer which is deposited over the semiconductor substrate and the temperature sensing elements. The temperature sensing elements are comprised of a refractory conductor, the refractory conductor has a temperature dependent electrical resistivity and has a width much less than its length.

Abstract: A bipolar transistor (408) is formed at a face of a semiconductor layer (152) of a first conductivity type. A first tank region (410) is formed in the semiconductor layer to be of a second conductivity type. A second tank region (412) is formed in the self-conductor layer to be of the first conductivity type and to be formed within the first tank region (410). At least one moat insulator region (210) is selectively grown on the face, with first, second, third, and fourth portions thereof being spaced apart. The first and second portions of the moat insulator region (210) self-align the implantation of a collector contact region. The second and third portions of the moat insulator region (210) self-align the implantation of an emitter. The third and fourth portions of the moat insulator region (210) self-align the implantation of a base contact region.

Abstract: A differential emitter coupled logic circuit having an output and a compliment of the output, the circuit comprising: a first emitter coupled transistor pair (Q17 and Q18); a second emitter coupled transistor pair (Q19 and Q20); a third emitter coupled transistor pair (Q25 and Q26); a fourth emitter coupled transistor pair (Q33 and Q34); a filch emitter coupled transistor pair (Q37 and Q38); and a sixth emitter coupled transistor pair (Q35 and Q36).

Abstract: A process chamber purge module (56) is provided, including a stack module (60) and a process chamber liner (62). The stack module comprises a plurality of quartz plates (100, 110, and 116) having flow apertures to permit radial and axial flow of a purge gas to the backside of a semiconductor wafer (18). The process chamber liner (62) isolates the process chamber walls from the process chamber process environment by flowing between the liner and the walls a portion of the purge gas. Process chamber liner (62) comprises a quartz cylindrical collar that operates to decouple the process chamber (16) process environment (20) from the process chamber collar walls (42). The stack module (60) decouples the process chamber optical/vacuum quartz window (64) from the semiconductor wafer (18) during a heated semiconductor wafer fabrication process. By flowing purge gas to the backside of the semiconductor wafer (18), the present invention prevents reactive process gas interaction with the semiconductor wafer backside.

Abstract: The present invention is a dynamic type semiconductor memory device comprising a plurality of memory cells (not shown), plural pairs of bit lines, a first sense amplifier (20), arranged for each of the plural pairs of bit lines, for amplifying a bit line signal. A pair of data input/output lines extracts data from a pair of bit lines. A second sense amplifier (22), is arranged for each of said plural pairs of bit lines and consists of first and second driver MOS transistors (52 in FIG. 3) gates of which are connected to the pair of bit lines. The second sense amplifier is activated when said first sense amplifier is activated, for amplifying signals of the pair of data input/output lines. First and second column selecting transistors (30 in FIG. 2) are inserted between the pair of data input/output lines and the second sense amplifier and gates of which are connected to a column selecting line. A first write transistor (54 in FIG.

Abstract: One embodiment of the present invention is a digital circuit (10) for providing glitch-free data in an asynchronous environment, the circuit comprising: an input circuit (11) for accepting data; combinational logic circuitry (12) for accepting the data from the input circuit (11 ) and manipulating the data to provide output data, wherein a delay in data flow occurs while the combinational logic manipulates the data; and an output circuit (14) for accepting the output data at a predetermined period after the receipt of data by the input circuit. Preferably, the predetermined period is at least as long as the delay in data flow.

Abstract: An electrically-erasable, electrically-programmable read-only memory cell is formed in a layer of semiconductor (1062) of a first conductivity type. A first heavily doped region (1022) and a second heavily doped region (1024) are formed in semiconductor layer (1062) to be of a second conductivity type opposite the first conductivity type. First heavily doped region (1022) is spaced from second heavily doped region (1024) by a first channel (1026). A gate conductor (1028) insulatively overlies channel (1026) for selectively controlling the conductance thereof. A third heavily doped region (1036) is formed in semiconductor layer (1062) to be of the second conductivity type. Third heavily doped region (1036) is separated from second heavily doped region (1024) by a channel (1038) and tunneling window (1040). A thin oxide tunneling window (1040) is formed overlying a portion of lightly doped region (1072) in channel (1038).

Abstract: A bipolar transistor is disclosed which substantially reduces prior art problems associated with current crowding by maximizing the active periphery of the transistor's emitter [10].

Abstract: An embodiment of the present invention is a method of fabricating power and non-power devices on a semiconductor substrate, the method comprising: forming alignment marks in the substrate (100); introducing a dopant of a first conductivity type into the substrate to form high-voltage tank regions ( 103); annealing the dopants (105); introducing dopants of the first conductivity type and a second conductivity type in a region in the high-voltage tank region (109); annealing the dopants of the first and the second conductivity type to form a second region within a third region, both within the high-voltage tank region, due to the different rates of diffusion of the dopants (110); and forming gate structures after the annealing of the dopants of the first and second conductivity types (122).

Abstract: A BICMOS latch driver L/D is used to implement a BICMOS gate array memory cell (FIG. 2b). The memory cell includes a latch formed by cross-coupled invertors (INV1 and INV2). The driver stage is formed by an NPN transistor Q0 and an n-channel transistor MN3. The relatively stronger bipolar transistor is used to pull the output of the BICMOS latch/driver HI, while, for most applications, the relatively weaker n-channel device has sufficient strength to pull the output low. A WRITE port (WP) that interfaces to the WRITE bitline, and a READ port (RP) that interfaces to the READ bitline.

Abstract: A thin reflective cylindrical baffle [20] in a radiant lamp heater is provided in the space below a plurality of heating bulbs [2,4,6] (arranged in a center position and around a middle and outer ring) and above a quartz window [12]. The baffle diameter is such that it fits within the annular space between the middle [4] and outer [6]ring of bulbs. The baffle which blocks a predetermined amount of light generated by the lamp bulbs [20] allows improved controllability of wafer temperature profile--for a wafer heated by a radiant lamp heater.