Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after etch back. In a silicon-on-insulator (SOI) device, dummy active areas are inserted between the active areas in order to maintain the thickness of the refill layer between the mesas to insure proper isolation between the active devices. The technique is also applicable to non-SOI devices.

Abstract: A technique of producing a semiconductor device or integrated circuit produces a planarized refill layer which has a more uniform thickness after polishing, such as by chemical-mechanical polishing (CMP). Dummy active areas are inserted between active areas in that portion of the substrate which would normally be occupied by a field oxide in order to reduce to "dishing" that occurs during CMP in these areas. The dummy active areas can take the shape of a large block, a partially or completely formed ring structure or a plurality of pillars the area density of which can be adjusted to match the area density of the active areas in that region of the substrate. The design rule for the pillars can be such that no pillars are placed where polycrystalline silicon lines or first level metallization lines are to be placed in order to avoid parasitic capacitances.

Abstract: A system for testing and adjusting threshold voltages in flash EEPROMs is disclosed. The system includes a memory cell array (5) comprising a plurality of cell columns. Each cell column includes a plurality of memory cells (10). Each memory cell (10) has a control gate terminal (14), a drain terminal (12) and a source terminal 11. A control system comprising a wordline decoder (16), a column decoder (19) and a microprocessor (21) applies selected voltages to the respective terminals of the memory cells (10), and selects one of the plurality of cell columns for compaction verification. A detector (30) determines whether any one of the memory cells (10) of the selected cell column has a threshold voltage below a predetermined positive voltage, and supplies an output signal to the control system. The control system increases respective threshold voltages of the memory cells (10) of the selected cell column in response to the output signal of the detector (30).

Abstract: An apparatus integrating pad conditioning device (44) with a wafer carrier device (24) for chemical-mechanical polishing applications includes an attaching mechanism (45) for associating conditioning device (44) with wafer carrier device (24). Conditioning surface (84) of conditioning device (44) conditions the polishing pad associates with attaching mechanism (45). Carrier device (24) receives and holds wafer (42) so that wafer (42) and conditioning surface (44) contact the polishing pad (42) to simultaneously condition polishing pad (26) and polish wafer (42).

Abstract: Apparatus (10, 30, 60) and a method for generating low energy electrons (26, 46) for neutralizing charges (16, 36, 66) accumulated on a wafer (14, 34, 64) is provided. The apparatus includes a photocathode (24, 44, 67) located within a predetermined distance from the wafer (14, 34, 64), and a light source (20, 40, 70, 76, 86) operable to emit a light (22, 42, 72, 78, 88) striking the photocathode (24, 44, 67), the photocathode (24, 44, 67) generating a cloud of low energy electrons (26, 46) with a narrow energy distribution near the wafer (14, 34, 64).

Abstract: An improved chemical mechanical polishing method of and apparatus (30) for performing CMP process on a plurality of semiconductor devices includes a plurality of carrier devices (14), each for receiving one of the plurality of semiconductor devices (22) such as a semiconductor wafer. A plurality of polishing pad mechanisms (12) associate with each of the carrier devices (14) so that each of the plurality of polishing pad mechanisms (12) separately and approximately simultaneously polishes one of the plurality of semiconductor devices (22). Control means controls the movement of each of the plurality of polishing pad mechanisms (12) relative to the associated semiconductor device (22) so that the semiconductor device (22) is separately polished.

Abstract: An apparatus (10) is provided for controlling the flow of a fluid. The apparatus (10) includes a housing (12) having an inlet port (14), an outlet port (16), and a bypass port (18). A throughput block (26) is contained within the housing (12). The throughput block (26) has a number of cylinders (28) formed therein. A number of pistons (34) are received within the cylinders (28). Each piston (34) can move within a corresponding cylinder (28) between a first position and a second position. En the first position, the piston (34) prevents fluid communication between the inlet port (14) and the outlet port (16) and allows fluid communication between the inlet port (14) and the bypass port (18). In the second position, the piston (34) prevents fluid communication between the inlet port (14) and the bypass port (18) and allows fluid communication between the inlet port (14) and the outlet port (16).

Abstract: An EPROM disclosed in this specification includes a unique floating gate memory cell which may be charged using a reduced voltage level. The memory cells are fabricated using a mask to define the buried source, drain, and field oxide regions of the memory cell. After removal of the mask, field oxide regions are formed and a floating gate is fabricated which extends beyond the boundaries of the channel region for the floating gate field effect transistor memory cell. This extended floating gate provides additional capacitive coupling between the gate/word line and the floating gate while maintaining the same capacitive coupling between the floating gate and the channel of the floating gate field effect transistor memory cell. One embodiment discloses a silicide which is applied to the buried source and drain regions. The silicide is fabricated by forming a slot through the field oxide, forming a silicide on the diffused regions, refilling the slot with an oxide, and planarizing the resulting structure.

Abstract: An embodiment of the instant invention is a method of forming a conductive structure over a semiconductor wafer, the method comprising the steps of: forming a first aluminum layer (14, 24) of a thickness; forming a conductive layer (18,28) of a material which is not readily etched by aluminum-etching etchants on the first aluminum layer, the conuctive layer having a thickness; forming a second aluminum layer (20, 30) on the conductive layer, the second aluminum layer having a thickness; patterning and etching the second aluminum layer thereby exposing a portion of the conductive layer; etching the exposed portion of the conductive layer thereby exposing a portion of the first aluminum layer; etching the exposed portion of the first aluminum layer; subjecting semiconductor wafer to a thermal step thereby diffusing the material in the conductive layer from the conductive layer into the first and second aluminum layers; and wherein the thickness of the conductive layer is much thinner than the thicknesses of the

Abstract: An ultimate low k (k=1) gap structure for high speed logic devices in which the sidewalls fully or partially cover the gaps between the interconnects by dry etching the already formed aluminum interconnects after the photoresist has been stripped. This method is particularly useful for the subsequent deposition of silicon dioxide and for forming air gaps.

Abstract: A method of removing inorganic contamination (contamination 104 of FIGS. 2a-2b) from a layer (layer 102) overlying a substrate (substrate 100), the method comprising the steps of: removing the layer overlying the substrate with at least one removal agent; reacting the inorganic contamination with at least one conversion agent, thereby converting the inorganic contamination; removing the converted inorganic contamination by subjecting it to at least one solvent agent, the solvent agent included in a first supercritical fluid; and wherein the converted inorganic contamination is more highly soluble in the solvent agent than the inorganic contamination.

Abstract: A method of removing inorganic contamination from substantially the surface of a semiconductor substrate, the method comprising the steps of: reacting the inorganic contamination with at least one conversion agent, thereby converting the inorganic contamination; removing the converted inorganic contamination by subjecting it to at least one solvent agent, the solvent agent is included in a first supercritical fluid (preferably supercritical CO.sub.2); and wherein the converted inorganic contamination is more highly soluble in the solvent agent than the inorganic contamination.

Abstract: A virtual sensor based monitoring and fault detection/classification system (10) for semiconductor processing equipment (12) is provided. A plurality of equipment sensors (14) are each operable to measure a process condition and provide a signal representing the measured process condition. A plurality of filtering process units (16) are each operable to receive at least one signal from the plurality of equipment sensors (14) and to reduce data represented by the at least one signal and provide filtered data. A plurality of virtual sensors (24) are each operable to receive the filtered data. The plurality of virtual sensors (24) model states of the processing equipment (12) and a work piece in the processing equipment (12). Each virtual sensor is operable to provide an output signal representing an estimated value for the modeled state.

Abstract: The capacitance type gaseous sensing device (10) includes a first electrode layer (12) formed on a semiconductor substrate layer (14). A seed layer (16) is formed on the first electrode layer (12). A reorganized layer (18) is formed on the first electrode layer (12) through interaction with the seed layer (16) to form a porous sensing layer. A second electrode layer (20) is formed on the reorganized layer (18). The reorganized layer (18) absorbs gaseous elements that change the dielectric constant of the capacitance type sensor device (10). A change in the dielectric constant causes a change in the capacitance of the reorganized layer (18) as measured across the first electrode layer (12) and the second electrode layer (20).

Abstract: One embodiment of the instant invention is a method of abruptly terminating etching of a dielectric layer on a semiconductor wafer, the method comprising the steps of: removing the semiconductor wafer from the etchant, the etchant is held a first temperature; and rinsing the semiconductor wafer in a rinse solution that is at a second temperature, the second temperature is at least 5.degree. C. colder than the first temperature. Preferably, the dielectric layer is comprised of: TEOS, BPSG, PSG, thermally grown oxide, and any combination thereof. Preferably, first temperature is approximately 25.degree. C. and the second temperature is approximately 0.degree. to 5.degree. C.; or the first temperature is approximately 70.degree. to 90.degree. C. and the second temperature is approximately 10.degree. to 30.degree. C. Preferably, the etchant is comprised of a buffered or unbuffered HF acid, and the rinse solution is comprised of deionized water. The second temperature is, preferably, at least 15.degree. C.

Abstract: An embodiment of the instant invention is an ESD protection circuit (100) for protecting a circuit from negative stress, the ESD protection circuit comprising: a first terminal (102); a second terminal (104), the circuit to be protected connected between the first and the second terminals; a substrate (202) of a first conductivity type; a first doped region (206) of a second conductivity type opposite the first conductivity type and formed in the substrate, the first doped region forming the source of a transistor; a second doped region (208) of the second conductivity and formed in the substrate spaced from the first doped region by a channel region, the second doped region forming the drain of the transistor; a first diode region (210) of the first conductivity type and formed in the substrate, the first diode region being spaced a minimum distance from the second doped region and wherein the first diode region forms the anode of a diode (108) and the second doped region forms the cathode of the diode; and

Abstract: A merged BiCMOS device 10 having a bipolar transistor 60 and a PMOS transistor 64 formed in the same well region 18. Bipolar transistor 60 is comprised of an emitter electrode 30, base region 26, and collector region formed by well region 18. Emitter electrode 30 is separated from base region 26 by thick oxide 24. Tungsten-silicide layer 32 covers emitter electrode 30. PMOS transistor 64 comprises source/drain regions 52 and 52a, gate electrode 40, and gate oxide 36. PMOS transistor 64 may optionally comprise LDD regions 44. Source/drain region 52a is in contact with base region 26. If desired, the emitter electrode 30 and gate electrode 40 may be silicided.

Abstract: One embodiment of the instant invention is an electrostatic discharge protection device (10) which includes a field-effect transistor, the field-effect transistor comprising: a substrate (12) of a first conductivity type and having a surface and a backside; a gate structure (18) insulatively disposed on the substrate; a blocking region (30) disposed on the substrate and adjacent to the gate structure; a lightly-doped region (32) of a second conductivity type opposite the first conductivity type and disposed within the substrate and beneath the blocking region; a channel region (14) disposed within the substrate, under the gate structure, and adjacent the lightly-doped region; a first doped region (38) of the second conductivity type and disposed within the substrate and adjacent to the lightly doped region, the first doped region spaced away from the channel region by the lightly-doped region; and a second doped region (22) of the second conductivity type and disposed within the substrate, the second doped re

Abstract: One embodiment of the instant invention is a method of preventing the formation of silicic acid on exposed silicon of an electronic device formed on a silicon wafer and having silicon features, the method comprising: removing a portion of oxide (step 302) formed on the silicon wafer thereby exposing at least some portion of the silicon substrate or the silicon features; cleaning the silicon wafer by subjecting the silicon wafer to an ozonated solution (step 304), preferably deionized water; and drying the silicon wafer (step 306). Preferably, a thin oxide is formed on the silicon wafer during the step of subjecting the wafer to the ozonated solution. The thin oxide is, preferably, on the order of approximately 6 to 20 .ANG. thick. After removing said portions of oxide and thereby exposing portions of said silicon wafer and/or silicon feature, the exposed silicon becomes hydrophobic.

Abstract: A feature (24) of a semiconductor device (10) is formed in a photoresist (14). To accurately measure a dimension (26) of the feature (24), portions of the photoresist (14) are removed to provide a reduced thickness (34) of the photoresist (14). The ratio between the reduced thickness (34) and the dimension (26) allows for more accurate dimension measurement of the feature (24) of the semiconductor device (10).