Abstract: An embodiment of the instant invention is a method of etching a conductive structure comprised of copper and overlying a semiconductor substrate, the method comprising the step of: subjecting the conductive structure to a combination of plasma, an etchant, and a gaseous aluminum source. Preferably, the conductive structure is comprised of aluminum and copper (more preferably, it is comprised of aluminum and 1 to 4% by weight copper) or it may be substantially comprised of substantially pure copper. In addition, the etchant is preferably introduced into the process chamber in a gaseous state and is comprised of Cl.sub.2. The gaseous aluminum source may be comprised of: DMAH, trimethylaluminum, dimethylalane, trimethylaminealine, dimethylethylaminealane, dimethylethylaminedimethylalane, or AlCl.sub.3.

Abstract: A double sided single inline memory module (20) comprising a substrate (70) having a plurality of openings (86) and first and second surfaces (92, 94), a plurality of pads (82) being integral with the substrate (70) and extending into the opening (86), a plurality of chips (50) adhered to the substrate (70) having bonding pads (120), wire bonding (80) electrically connecting at least one of the bonding pads (120) to at least one of the pads (82) and potting material (90) encapsulating the wire bonding (80) and filling the opening (86) is disclosed.

Abstract: One embodiment of the instant invention is a charge-induced damage protection device (100 or 500) for protecting a semiconductor device (200) which is formed on a common substrate with the protection device, the protection device comprising: a region in the substrate; and wherein the region is accessible to electromagnetic energy during processing in which charges may collect on conductive material such that the protective device turns on at a lower voltage due to introduction of the electromagnetic energy to the region so as to protect the semiconductor device from the charge-induced damage. Preferably, the protection device is selected from the group consisting of: a diode, a thyristor, a bidirectional thyristor, a bipolar transistor, and a polymer that becomes more conductive upon being illuminated by electromagnetic energy.

Abstract: A lead frame (10) is connected over an integrated circuit (40) by adhesives (42) and (44). Each lead conductor (16) and (18) of the lead frame (10) has the identical geometric area in order to provide identical capacitances. A metal shield may be provided on adhesives (42) and (44) to provide noise shielding for the integrated circuit (40).

Abstract: A method for manufacturing a column grid array semiconductor package (10, 210) may include the steps of providing a substrate material (14, 114, 214) having a first side (16, 116) and a second side (18), forming a plurality of holes (36, 136, 236) in the substrate (14, 114, 214), forming contacts (24, 124,) on the first surface (16, 116) of the substrate (14, 114, 214), filling the plurality of holes (36, 136, 236) with a conductive material (32, 132, 232) to an extent that an extension portion (28, 128, 228) is formed on the second side (18) of the substrate (14, 114, 214) to which an electrical contact may be made. The extension portion (28, 128, 228) may be coated with a capping material (40, 140, 240). The holes (36, 136, 236) may be filled with the conductive material (32, 132, 232) by placing a material (146, 246) over the hole (36, 136, 236) on the first side (16, 116) of the substrate (14, 114, 214) and filling the holes (36, 136, 236) with the conductive material (32, 132, 232).

Abstract: A method for making a memory cell (10) in a process in which both an n-channel MOS transistors (12) and a p-channel transistor (44) are formed in a semiconductor substrate (30) is presented. The method includes implanting an impurity (40) into a region of the substrate (30) to form a part of a depletion NMOS memory capacitor (21) to be associated with the n-channel MOS memory transistor (12). The implant is performed concurrently with a patterned implant with the same impurity to adjust the threshold and punch-through of the p-channel transistor (44).

Abstract: An embodiment of the instant invention is a method of fabricating a conductive structure for electrically connecting one portion of a semiconductor device to another portion of the device, the method comprising the steps of: providing a continuous liner layer (step 104) of the semiconductor substrate, the liner layer comprised of CVD Al; forming a first conductor (step 106) on the liner layer, the first conductor formed using a source whose output power is in the range of 1 to 5 kW; and forming a second conductor (step 108) on the first conductor, the second conductor formed using a source whose output power is in the range of 10 to 20 kW. Preferably, the conductive structure is selected from the group consisting of: contact, via, and trench. In an alternative embodiment, a nucleation layer is formed (step 104) beneath the continuous liner layer. The nucleation layer is, preferably, comprised of titanium or a Ti/TiN stack.

Abstract: This is a curing method of low-k dielectric material in a semiconductor device and system for such. The method may comprise: depositing metal interconnection lines; depositing the low-k dielectric material layer over the lines; and curing the low-k dielectric material layer with a heating lamp for less than 10 minutes, wherein the heating lamp provides optical radiation energy in the infrared spectral range of about 1 micron to 3.5 microns in wavelength. The heating lamp may be a tungsten-halogen lamp.

Abstract: A high-k dielectric capacitor structure and fabrication method that incorporates an adhesion promoting etch stop layer 200 to promote adhesion of the bottom electrode 220 to the interlevel dielectric layer 210 and to provide a well controlled, repeatable and uniform recess prior to the dielectric 230 deposition. By using a sacrificial layer 200, for example silicon nitride (Si3N4), this layer can act as an etch stop during the recess etch to eliminate parasitic capacitance between adjacent capacitor cells A and B and can promote adhesion of the bottom electrode material 220 to the substrate 210.

Abstract: A contact (26) to a substrate (12) is formed using a first stopping layer (14), an insulating layer (16), and a second stopping layer (18). The second stopping layer (18) promotes a more accurate and controlled removal of the first stopping layer (14). A self-aligned contact (122) may be formed in a similar manner using a first stopping layer (110), an insulating layer (112), and a second stopping layer (114).

Abstract: A suppression electrode assembly (18) comprises an electrode suppression plate (40) constructed of a material having substantial strength and durability and has an aperture seat (76) with an opening (72) defined therein. An aperture insert (80) constructed from graphite is slidably engageable with the aperture seat (76). The aperture insert (80) defines an elongated slit (84) which is in general alignment with the aperture seat opening (72) when the aperture insert (80) is installed in the seat (76).

Abstract: Heteroepitaxy of lattice-mismatched semiconductor materials such as GaAs (110) on silicon (102) is accomplished by formation of a defect annihilating grid (104) on the silicon (102) prior to the epitaxy of the GaAs (110).

Abstract: A semiconductor surface measurement system (100) is disclosed. In this system, a plurality of wafers (106), each having an exposed surface, are held by a wafer positioning system (104), which sequentially moves the wafers into a measurement zone. A wafer position detection system (124) detects the position of a selected wafer, and generates an output signal indicating the position of the selected wafer. A surface measurement apparatus (114 through 121, 130 through 142) measures a property of the exposed surface of the selected wafer (106) in response to the output signal of the wafer position detection system (124) when the selected wafer is in the measurement zone. The disclosed surface measurement system (100)may be used to gather real-time data concerning surface properties such as composition, roughness and epilayer thickness during multi-wafer semiconductor processing.

Abstract: A high density single inline memory module (140) comprising a printed circuit board (132) and at least one integrated circuit module (130) attached to the first side (134) of the printed circuit board (132), wherein the integrated circuit modules (130) each including first and second integrated circuit packages (30) stackably and electrically connected together is disclosed.

Abstract: A method is provided for forming a piezoelectric layer with improved texture. In the method, a metallic material is evaporated. A noble gas is combined with a reactant gas. An atomic reactant gas flow is generated from the combined gas using a plasma source. The atomic reactant gas flow is introduced to the evaporated metallic material in the presence of a substrate under molecular flow pressure conditions to form a piezoelectric layer with improved texture on the surface of the substrate.

Abstract: An integrated circuit package (30) including a substrate (70) having an opening (86) and first and second surfaces(92, 94), a plurality of pads (100) disposed on the first and second surfaces (92, 94) having disposed thereon solder balls (150) electrically connected by a via (84) that provides the end-user with flexibility in the location of a power supply Pin (96) is disclosed.

Abstract: An embodiment of the instant invention is a method of optimizing an I/O circuit formed on a substrate with regards to an overvoltage or ESD event wherein the I/O circuit comprises at least one MOS device which has I-V characteristics, the method comprising the steps of: extracting selective electrical characteristics of the MOS device while the MOS device is operating in the avalanche and snapback regions of the I-V characteristics of the MOS device; characterizing the MOS device for the overvoltage or ESD event based on the electrical characteristics of the MOS device under standard operating conditions, the MOS device being comprised of a parasitic bipolar transistor and the substrate having a resistance; and wherein the I/O circuit is optimized for the overvoltage or ESD events by modifying the I/O circuit based on the electrical characteristics of the MOS device in conjunction with the characterization of the parasitic bipolar transistor and the substrate resistance.

Abstract: A dry etch method for removing TixNy films by using a remote plasma to excite a oxygen+fluorine source gas mixture, generating active species that etch TixNy with minimum attack to other materials. In particular, an isotropic dry etch can be used for the selective removal of TiN in W/TiN gate structures without gate oxide damage. This etch also permits selective stripping of titanium nitride in a salicidation process.

Abstract: An apparatus for producing silicon crystals (24) having highly uniform characteristics from a silicon melt (22) comprising a furnace (12), a crucible (14) disposed within the furnace (12) for containing the silicon melt (22), a heater (20) disposed around the crucible (14) for heating the silicon melt (22) and a pair of cusp magnets (28, 30) disposed around the furnace (12) and spaced a distance apart from one another such that the distance between the cusp magnets (28, 30) is variable.

Abstract: A method is provided for forming a piezoelectric layer with improved texture. In the method, a seed material is deposited on a substrate (12) at a low deposition rate to form a seed layer (16). The low deposition rate may be a rate in the range of 10.0-150 nanometers per hour. A piezoelectric material is deposited on the seed layer at a high deposition rate to form a bulk piezoelectric layer (20) having improved texture. The high deposition rate can be a rate in the range of 500-5000 nanometers per hour.