Abstract: An electrostatic discharge (ESD) corner clamp is connected to a positive ESD rail that has a steady first voltage, such as 2.6V, and can be driven to a larger second voltage, such as 4.3V. The ESD corner clamp provides 5V tolerance by utilizing a keep off circuit that prevents the corner clamp from triggering when the voltage on the positive ESD rail changes from the first voltage to the second voltage.

Abstract: A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

Abstract: A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown voltage of the zener diode is set to a desired value within a range of values by modifying the area of a new opening in one of existing masks.

Abstract: The safe operating area of a high-voltage MOSFET, such as a lateral double-diffused MOS (LDMOS) transistor, is increased by using transistor cells with an X-shaped body contact region and four smaller source regions that adjoin the body contact region. The X-shaped body contact region lowers the parasitic base resistance of the transistor, thereby increasing the safe operating area of the transistor.

Abstract: An ESD protection circuit that can be easily configured to provide ESD event protection against a range of ESD event voltages. The circuit is also compatible with high frequency ICs. The ESD protection circuit includes an input terminal configured to receive an ESD event signal and a diode sub-circuit. The diode sub-circuit includes at least one diode (e.g., either a single diode or a plurality of diodes connected in series or parallel configuration), a diode input node and a diode output node. The diode sub-circuit is configured to receive an ESD event signal from the input terminal and to operate under forward bias conditions to provide a diode output signal at the diode output node. The circuit also includes a bipolar junction transistor (e.g., a Si—Ge bipolar junction transistor) with a base, a collector and an emitter. The emitter is configured to receive the ESD event signal from the input terminal, while the base is configured to receive the diode output signal from the diode output node.

Abstract: The formation of intermetallic residue regions during the formation of a semiconductor metal layer, which has a base metal layer and a cap metal layer formed on the base metal layer, is substantially reduced by forming a layer of oxide on the base metal layer before the cap metal layer is deposited.

Abstract: The holding voltage (the minimum voltage required for operation) of a triac is increased to a value that is greater than a dc bias on to-be-protected nodes. The holding voltage is increased by inserting a voltage drop between each p+ region and a to-be-protected node. As a result, the triac can be utilized to provide ESD protection to power supply pins.

Abstract: A split-gate FLASH memory cell is formed with a floating gate that has a tip in the middle of the floating gate. The method of the present invention forms the tip to have a substantially constant radius of curvature, tip angle, and distance to the overlying tunneling oxide. As a result, the tip of the present invention increases the localized enhancement of the electric field.

Abstract: The crowbar current in a driver inverter, which has a pair of complementary driver transistors, is substantially reduced by adjusting the turn on and turn off times of the p-channel and n-channel driver transistors such that each driver transistor turns on after the other driver transistor has been turned off.

Abstract: The upper epitaxial layer of a bipolar transistor has a silicon germanium layer and an overlying cap layer. The upper epitaxial layer includes an intrinsic emitter region and a base region. The silicon germanium layer is spaced apart from the intrinsic emitter region, and lies outside of the depletion region associated with the junction between the intrinsic emitter region and the base region.

Abstract: Effects of glitches on the data line which can cause an I2C bus (or SMBus) interface to invalidate a detected I2C start command or to erroneously detect an I2C start command, which occurs when the data signal transitions from a logic high to a logic low while the clock signal has a logic high, are reduced by detecting the logic state of the data signal when the clock signal next transitions from a logic high to a logic low.

Abstract: An apparatus for and method of self-testing a data packet communications device are disclosed. The apparatus tests the analog and digital transmission and reception capabilities of the device by generating a bit sequence, which the communications device forms into a packet, transmits the packet, then receives the packet and removes the bit sequence. The apparatus then compares the received bit sequence with another bit sequence and generates an error signal if the sequences fail to correspond. The bit sequence is generated by a linear feedback shift register which generates a pseudo-random sequence. Another linear feedback shift register generates another pseudo-random sequence which is compared to the first sequence. In this manner functional self-testing can be performed without an external testing device.

Abstract: A MOSFET structure for use in an ESD protection device that includes a semiconductor substrate (e.g., a silicon substrate) of a first conductivity type with a gate insulation layer (e.g., a gate silicon dioxide layer) thereon. A patterned gate layer overlies the gate insulation layer, source and drain regions of a second conductivity type are disposed in the semiconductor substrate, and an LDD source extension region of the second conductivity type is located adjacent to the source region. Furthermore, a channel region of the first conductivity type is disposed underneath the gate insulation layer and extends from the LDD source extension region to the drain region. The absence of an LDD drain extension region, combined with the presence of an LDD source extension region, provides for superior snap-back performance (i.e., a relatively low first breakdown voltage and a relatively low holding voltage).

Abstract: The complementary outputs of a master slave flip flop are made symmetric, with substantially zero timing skew over all process, voltage and temperature conditions. This is accomplished by utilizing a master latch and a pair of identical slave latches. Although the complementary outputs from the master latch have non-zero timing skew when the clock goes low, they have zero timing skew when the clock goes high. Thus the identical slave latches, whose outputs react to the master latch outputs only when the clock goes high, do not have any timing skew.

Abstract: The propagation delay time, power dissipation and silicon area of a double edge triggered flip flop are reduced by utilizing an inverter, a pair of latches, and a two-to-one multiplexer. A first latch outputs a first device signal in response to a first data signal when a clock signal is in a first logic state, and latches the logic state of the first device signal when the clock signal is in a second logic state. A second latch outputs a second device signal in response to a second data signal when the clock signal is in the second logic state, and latches the logic state of the second device signal when the clock signal is in the first logic state. The multiplexer controls the logic state of the flop output signal in response to the logic state of the first device signal when the clock signal is in the second logic state, and in response to the logic state of the second device signal when the clock signal is in the first logic state.

Abstract: Self-aligned floating gates are formed to have precisely defined lengths and positions. The floating gates are formed by first forming a number of shallow trench isolation regions that have substantially planar top surfaces that lie above the top surface of the semiconductor material. A layer of dielectric is formed on the semiconductor material, followed by the formation of a first layer of polysilicon. The first layer of polysilicon is then planarized so that the first layer of polysilicon is removed from the isolation regions. In subsequent steps, the polysilicon is again etched to form the floating gates. As a result of the planarization, the lengths of the floating gates are defined by the spacing between isolation regions, and the positions of the floating gates are precisely defined.

Abstract: A dual-sided semiconductor chip is formed on a wafer to have a low-resistance, electrically-conductive path through the wafer. By forming the conductive path through the wafer, elements on one side of the wafer can exchange signals (voltages and/or currents) with elements on the other side of the wafer.

Abstract: A low-power high-frequency bipolar transistor is formed to have a small self-aligned base region that reduces the base-to-collector capacitance, and small self-aligned base and emitter contacts that reduce the base-to-emitter capacitance and the base resistance. The base and emitter contacts are formed to have sub-lithographic feature sizes.

Abstract: An apparatus, method, and computer program improve scanning time by transferring data from a scanner to an associated device at a rate approximately equal to the average data transfer rate. The computer program sets a control variable that controls hardware in the scanner to adjust the scanning clock frequency, the vertical resolution, and the horizontal resolution to approach the average data transfer rate. Scanning at the average data transfer rate improves scanning time because restarts are eliminated.

Abstract: The holding voltage (the minimum voltage required for operation) of a low-voltage triggering silicon-controlled rectifier (LVTSCR) is increased to a value that is greater than a dc bias on a to-be-protected node. The holding voltage is increased by inserting a voltage drop between the to-be-protected node and the emitter of the pnp transistor of the LVTSCR. As a result, the LVTSCR can be utilized to provide ESD protection to power supply pins.