Patents Represented by Attorney Mark C. Pickering

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  • Centralized, double bandwidth, directional, shared bus communication system architecture
    Patent number: 7065593
    Abstract: A low-cost, high-speed, bus-based communication system is provided that includes a master electronics card, a number of slave electronics cards, and a backplane that interconnects the master and the slave electronics cards via a serial bus, a parallel bus and some common signals for clocking and synchronization.
    Type: Grant
    Filed: December 17, 2003
    Date of Patent: June 20, 2006
    Assignee: Tellabs Petaluma, Inc.
    Inventors: Paul Brian Ripy, Paul Edwin O'Connor, Amar Mohammed Othman
  • Silicon controlled rectifier structure with improved punch through resistance
    Patent number: 7064397
    Abstract: When a high-voltage, such as from an ESD pulse, is placed across a silicon controlled rectifier, which includes an NPN transistor and a PNP transistor that is connected to the NPN transistor, the likelihood of punch through occurring between two regions of the rectifier is substantially reduced by forming the collector of the NPN transistor between the emitter and collector of the PNP transistor.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: June 20, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Ann Concannon, Marcel Ter Beek
  • High-speed photon detector and method of forming the detector
    Patent number: 7057174
    Abstract: A photon detector capable of detecting gigahertz frequency optical signals utilizes a layer of photonic material that is formed adjacent to the coil of an inductor. When a pulsed light source is applied to the layer of photonic material, the photonic material generates eddy currents that alter the magnetic flux of the inductor. The signals can then be detected by detecting the change in the magnetic flux.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: June 6, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Michael Mian
  • Retaining clip for Anderson-type power connectors
    Patent number: 7056138
    Abstract: When a first pair of power connectors are inserted into a second pair of power connectors, the connectors are prevented from electrically and physically separating by a retaining clip that fits into the locking opening between the first pair of power connectors, and the locking opening between the second pair of power connectors.
    Type: Grant
    Filed: August 5, 2004
    Date of Patent: June 6, 2006
    Assignee: Tellabs Petaluma, Inc.
    Inventors: Mark Eugene Lewis, Christopher Michael Hankins, Jeffrey L. Wilson
  • Method of dicing a semiconductor wafer that substantially reduces the width of the saw street
    Patent number: 7052977
    Abstract: A semiconductor wafer is diced utilizing a method that etches down to the top surface of the semiconductor wafer a number of times, such as during and following the formation of the metal interconnect structure, and then thins the semiconductor wafer from the back side until the semiconductor wafer singulates.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: May 30, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Method of compensating for temperature changes and channel variations in a laser diode array to produce a substantially constant average optical power over temperature
    Patent number: 7054343
    Abstract: A relatively constant average optical power is provided over a user-defined range of temperatures by detecting the temperature, and adjusting the bias currents input to the laser diodes in an array of laser diodes based on the temperature and the channel loss of the channel connected to each diode.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 30, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Hsin-Ho Wu, Peter Deane
  • Multilevel metal interconnect and method of forming the interconnect with capacitive structures that adjust the capacitance of the interconnect
    Patent number: 7042092
    Abstract: The capacitance of a multilevel metal interconnect formed on a semiconductor substrate can be adjusted, and thereby optimized, to respond to signals from devices that are formed on the underlying substrate by forming capacitive structures in trenches which have been formed using the top metal layer as a mask.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: May 9, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Gated clock circuit with a substantially increased control signal delay
    Patent number: 7042267
    Abstract: A gated clock circuit outputs a gated clock signal in response to a master clock signal and a control signal that has a rising or falling edge that follows a rising edge of the master clock signal by a delay. The gated clock signal has a pulse width that is equal to, and in phase with, the pulse width of a master clock signal, while at the same time substantially increasing the maximum value of the delay.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: May 9, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Ronald Pasqualini
  • ESD protection circuit that can tolerate a negative input voltage during normal (non-ESD) operation
    Patent number: 7038898
    Abstract: An electrostatic discharge (ESD) protection circuit includes a diode that is connected between a pad and a power supply line, and a negative protection circuit that is connected between the pad and a ground line. The negative protection circuit allows the pad voltage to go below ground during normal (non-ESD) operation, and provides adequate ESD protection during an ESD event.
    Type: Grant
    Filed: February 24, 2005
    Date of Patent: May 2, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Ronald Pasqualini
  • Crystal oscillator circuit having a start-up time reduction circuit
    Patent number: 7034628
    Abstract: A quartz-crystal oscillator circuit substantially reduces the start-up time of the crystal oscillator circuit by utilizing a start-up time reduction circuit that adds additional gain to the crystal oscillator circuit during the start-up period, and removes the additional gain as the oscillator circuit nears steady state operation. Furthermore, the start-up time reduction circuit dynamically monitors the oscillation amplitude. If the build up of oscillation is interrupted, the additional gain will be re-applied.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: April 25, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Weiye Lu, Thomas Tse, Wai Cheong Chan
  • Power supply system and method that provides a low-cost approach to voltage scaling
    Patent number: 7030661
    Abstract: A low-cost approach to voltage scaling is realized by latching the output of a propagation delay detector, and inputting the latched output to a string digital-to-analog (DAC) converter. The string DAC generates a DC voltage in response to the latched values, which is fed back to the propagation delay detector.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: April 18, 2006
    Assignee: National Semiconductor Corporation
    Inventor: James Thomas Doyle
  • Level shifter that provides high-speed operation between power domains that have a large voltage difference
    Patent number: 7030678
    Abstract: The speed of a level shifter, which translates a first voltage in a first power domain to a second voltage in a second power domain, is increased by utilizing a first bipolar transistor to assist a first MOS transistor in pulling down the voltage on a first output node, and a second bipolar transistor to assist a second MOS transistor in pulling down the voltage on a second output node.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: April 18, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Alexander Burinskiy, Vladislav Potanin, Elena Potanina
  • Posture correcting device
    Patent number: 7024712
    Abstract: A seat pad is provided with a lower pad member and a upper pad member that is attached to the lower pad member by an adhesive. A pair of projections is formed at the front portion of the seat pad. A concave is defined between the projections. The upper surface of the seat pad is inclined to be lower toward the front end of the seat pad when the seat pad is put on a seat of a chair. When a person sits on the seat pad, a pelvis is held in a proper position, which improves the flow of blood and the behavior of nerve.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 11, 2006
    Assignee: Foot Techno, Inc.
    Inventors: Minoru Fujita, Ryoko Murotani
  • MOS transistor with serrated gate structures
    Patent number: 7023032
    Abstract: A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: James Thomas Doyle, Michael Angelo Tamburrino
  • Optical sensor that measures the light output by the combustion chamber of an internal combustion engine
    Patent number: 7022968
    Abstract: An optical sensor provides information about the burn of the fuel mixture in the combustion chamber of an internal combustion engine as well as the timing and waveform of the spark that ignites the fuel mixture in the combustion chamber. The optical sensor can be implemented as a stand-alone device, or incorporated into a spark plug.
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: April 4, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Michael Mian, Robert Drury
  • Heat exchanger with increased heat transfer efficiency and a low-cost method of forming the heat exchanger
    Patent number: 7011148
    Abstract: The efficiency of a heat exchanger is significantly improved by connecting walls to an air flow structure, which has first grooves formed in the top surface of the structure and second grooves formed in the bottom surface of the structure, that block off alternating ends of the first and second grooves such that a first air source can only flow through the first grooves and a second air source can only flow through the second grooves.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: March 14, 2006
    Assignee: Tellabs Petaluma, Inc.
    Inventors: Daniel J. Calanni, Lawrence M. Giacoma
  • Method of forming through-the-wafer metal interconnect structures
    Patent number: 7005388
    Abstract: A semiconductor die is formed in a process that forms a hole through the wafer prior to the formation of the contacts and the metal-1 layer of an interconnect structure. The through-the-wafer hole is formed by using a wafer with a <110> crystallographic orientation and a wet etch, such as with ethanol (KOH) or tetramethylammonium hydroxide (TMAH).
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: February 28, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Vladislav Vashchenko, Peter Johnson, Robert Drury
  • Content addressable memory with reduced instantaneous current and power consumption during a search
    Patent number: 7006400
    Abstract: The power required to search a content addressable memory (CAM) is substantially reduced by forming the CAM to have a number of CAM banks with a corresponding number of power switches that control power to the CAM banks, and then controlling the power to search the CAM banks one at a time.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: February 28, 2006
    Assignee: Tellabs Petaluma, Inc.
    Inventors: Paul Brian Ripy, Gary Jay Geerdes, Paul Edwin O'Connor, Christophe Pierre Leroy
  • Method and apparatus of allocating minimum and maximum bandwidths on a bus-based communication system with redundant communication circuits
    Patent number: 7003609
    Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to grant information which can be stored in a primary and a backup priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the primary or backup priority table that corresponds with the arbitration period, and the identities stored in the tables match only one requesting communication circuit, access to the bus is granted to the requesting communication circuit.
    Type: Grant
    Filed: September 23, 2003
    Date of Patent: February 21, 2006
    Assignee: Tellabs Petaluma, Inc.
    Inventors: Paul B. Ripy, Keith Q. Chung, Gary J. Geerdes, Christophe P. Leroy
  • Trim zener using double poly process
    Patent number: 6979879
    Abstract: In a zener zap diode device and a system for making such a device using a double poly process, p+ and n+regions are formed in a tub by means of p-doped and n-doped polysilicon regions, and a p-n junction is formed between the p+ region and an n-tub or between the n+ region and a p-tub. Cobalt or other refractory metal is reacted with silicon to form a silicide on at least the p-doped polysilicon region. By reverse biasing the p-n junction and establishing a sufficiently high zap current, the silicide can be forced to migrate across the junction to form a silicide bridge thereby selectively shorting out the p-n junction.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: December 27, 2005
    Assignee: National Semiconductor Corporation
    Inventors: Wipawan Yindeepol, Andy Strachan