Patents Represented by Attorney Mark C. Pickering

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  • PLL lock detector
    Patent number: 6744838
    Abstract: A detector digitally monitors and detects when an oscillating signal output by a phase-locked-loop (PLL) is locked to a reference signal input to the PLL. The PLL includes a phase frequency detector that outputs an up signal and a down signal that each has a pulse width. When the oscillating signal is locked to the reference signal, the pulse widths of the up and down signals are equal. The detector detects when the pulse widths are unequal, and outputs a lock status signal that indicates this condition.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: June 1, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Anand Dixit
  • Driver with bulk switching MOS power transistor
    Patent number: 6744288
    Abstract: A digital power supply system provides a supply voltage to semiconductor circuits. The power supply system utilizes a pulse width modulator to output a signal into a LC filter that generates a DC supply voltage. The width of the pulses output by the pulse width modulator are defined by an encoder that generates width information in response to a propagation delay detector that measures the propagation delay of a first clock signal when clocked by a second clock signal.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: June 1, 2004
    Assignee: National Semiconductor Corporation
    Inventors: James Thomas Doyle, Michael Angelo Tamburrino
  • Metal trace with reduced RF impedance resulting from the skin effect
    Patent number: 6740956
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: May 25, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Radiation hardened MOS transistor
    Patent number: 6730969
    Abstract: The drain-to-source field leakage current and the device-to-device field leakage current that are caused by radiation-induced hole trapping in the field oxide region are reduced in the present invention by forming the source and drain regions a distance apart from the edge of the field oxide region.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: May 4, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran, Reda Razouk
  • Output driver with over voltage protection
    Patent number: 6724595
    Abstract: An output driver obtains over voltage protection by utilizing a first transistor to pass signals from an internal node to an external node when the driver is transmitting data, and to isolate the internal node from the external node when the driver has stopped transmitting data. When the driver has stopped transmitting data, the voltage on the external node is subject to rising. The output driver also utilizes a second transistor and a resistance to ground to control the first transistor.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: April 20, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Khusrow Kiani
  • Deep submicron MOS transistor with increased threshold voltage
    Patent number: 6723593
    Abstract: A deep submicron MOS transistor is formed with multiple control gates by forming side wall control gates adjacent to the gate oxide spacers over heavily-doped regions of the source and drain regions. The side wall control gates can be used to substantially increase the threshold voltage of the transistor.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: April 20, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran, Reda Razouk
  • Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
    Patent number: 6703670
    Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: March 9, 2004
    Assignee: National Semiconductor Corporation
    Inventor: Terry Lines
  • Dual damascene metal trace with reduced RF impedance resulting from the skin effect
    Patent number: 6703710
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: March 9, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • Single poly bipolar transistor and method that uses a selectively epitaxially grown highly-boron-doped silicon layer as a diffusion source for an extrinsic base region
    Patent number: 6699741
    Abstract: A high frequency bipolar transistor that has a silicon germanium intrinsic base region is formed in a semiconductor fabrication process that forms the extrinsic base regions after the intrinsic base region has been formed. The extrinsic base regions are epitaxially grown single crystal silicon that is doped during the growth.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: March 2, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Alexei Sadovnikov, Christopher John Knorr
  • Silicon die with metal feed through structure
    Patent number: 6677235
    Abstract: A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: January 13, 2004
    Assignee: National Semiconductor Corporation
    Inventors: Visvamohan Yegnashankaran, Gobi R. Padmanabhan
  • Fully distributed slave ESD clamps formed under the bond pads
    Patent number: 6667870
    Abstract: The pads of a semiconductor die are protected from an electrostatic discharge (ESD) event by an ESD protection circuit that has a number of master corner clamps and a number of slave clamps that are controlled by the master corner clamps. The slave clamps are formed under the ESD plus and minus rings which, in turn, are formed under the pads, thereby providing a significant reduction in the height of the I/O cell, and improved ESD performance by reducing metalization IR drops.
    Type: Grant
    Filed: December 12, 2001
    Date of Patent: December 23, 2003
    Assignee: Natiional Semiconductor Corporation
    Inventor: Alan Erik Segervall
  • Method of inducing movement of charge carriers through a semiconductor material
    Patent number: 6660537
    Abstract: A conductive trace is formed over and insulated from a region of semiconductor material, such as a region adjacent to the n+ region of an n+/p− photodiode, and a sawtooth current is made to flow through the conductive trace. The sawtooth current induces charge carriers to move through the semiconductor material to a collection region in the semiconductor material.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Kyuwoon Hwang
  • Slurry dispenser that outputs a filtered slurry to a chemical-mechanical polisher at a constant flow rate over the lifetime of the filter
    Patent number: 6659848
    Abstract: The slurry used in a chemical-mechanical polisher is passed through a filter, and output at a constant flow rate throughout the lifetime of the filter by measuring the flow rate of the slurry, comparing the measured flow rate to a reference set point rate, and adjusting the pump speed of a slurry pump when the measured flow rate differs from the reference set point rate.
    Type: Grant
    Filed: July 29, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corporation
    Inventors: David Linn Craig, Matthew Gautreau
  • Semiconductor-based spiral capacitor
    Patent number: 6661079
    Abstract: Increased capacitance per unit of area with reduced series resistance and inductance is provided by a semiconductor-based capacitor with a spiral shape. The capacitor utilizes a plurality of patterned metal layers that each have a first trace with a spiral shape and a second trace with a spiral shape. The second trace is formed between the loops of the first trace, and around the first trace.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Simon Bikulcius
  • Varactor and method of forming a varactor with an increased linear tuning range
    Patent number: 6653716
    Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: November 25, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Pascale Francis, Peter J. Hopper
  • Bipolar transistor with a silicon germanium base and an ultra small self-aligned polysilicon emitter and method of forming the transistor
    Patent number: 6649482
    Abstract: A low-power bipolar transistor is formed to have a silicon germanium base region, an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The silicon germanium base region increases the speed of the transistor, while the small extrinsic emitter region reduces the maximum current that can flow through the transistor, and the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: November 18, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Abdalla Aly Naem
  • Bandgap tuned vertical color imager cell
    Patent number: 6646318
    Abstract: A combination of materials is used to form the photodiodes of a vertical color imager cell. The materials used to form the photodiodes have different band gaps that allow the photon absorption rates of the photodiodes to be adjusted. By adjusting the photon absorption rates, the sensitivities of the photodiodes and thereby the characteristics of the imager can be adjusted.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: November 11, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer
  • Method of forming photonic crystals using a semiconductor-based fabrication process
    Patent number: 6633427
    Abstract: A photonic crystal is formed on a semiconductor substrate using a semiconductor-based fabrication process by forming a number of alternating layers of material that have different dielectric constants. The layers of material are then etched to form a number of spaced-apart stacks of alternating layers of material. An interstack material is then formed between the stacks.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: October 14, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Waclaw C. Koscielniak
  • Method of programming a splity-gate flash memory cell with a positive inhibiting word line voltage
    Patent number: 6621736
    Abstract: A split-gate flash memory array is programmed, in part, by applying a programming voltage to the row of cells that include the to-be-programmed cells, and an inhibiting voltage to the row of cells that share the same source line as the row that includes the to-be-programmed cells. The inhibiting voltage is greater than zero and less than the programming voltage.
    Type: Grant
    Filed: March 5, 2002
    Date of Patent: September 16, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Yuri Mirgorodski, Pavel Poplevine, Mark W. Poulter
  • 5V tolerant corner clamp with keep off circuit and fully distributed slave ESD clamps formed under the bond pads
    Patent number: 6621680
    Abstract: The pads of a semiconductor die are protected from an electrostatic discharge (ESD) event by an ESD protection circuit that has a number of master clamps and a number of slave clamps that are controlled by the master clamps. The slave clamps are formed under the ESD plus and minus rings which, in turn, are formed under the pads, thereby providing a significant reduction in the height of the I/O cell, and improved ESD performance by reducing metalization IR drops. The master and slave clamps provide 5V tolerance by utilizing a keep off circuit that prevents the master clamp from triggering when the voltage on the positive ESD rail changes from a first non-ESD voltage to a second non-ESD voltage.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: September 16, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Alan Erik Segervall