Abstract: A MOS transistor and subsurface collectors can be formed by using a hard mask and precisely varying the implant angle, rotation, dose, and energy. In this case, a particular atomic species can be placed volumetrically in a required location under the hard mask. The dopant can be implanted to form sub-silicon volumes of arbitrary shapes, such as pipes, volumes, hemispheres, and interconnects.

Abstract: The speed of a level shifter is increased by utilizing an additional transistor to pull down the voltage on a first intermediate node, and an additional transistor to pull down the voltage on a second intermediate node. In addition, a precharge circuit is utilized to precharge the voltage on the first and second intermediate nodes to further increase the speed of the level shifter.

Abstract: A leakage compensation circuit compensates for current changes that result from bulk leakage currents that occur when a current source transistor is connected to a number of switches. A leakage current flows out of a switch, while a compensation transistor connected to the switch sinks a current substantially equal to the leakage current.

Abstract: An inductor is formed from the interconnect structure of a semiconductor chip, using the vias and metal regions to form up and down segments of a loop, and horizontal metal lines to form the top and bottom segments of the loop. In addition, a second inductor can be formed between or under the first inductor to form an inductive system, such as a transformer.

Abstract: The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and drain regions in a layer of composite material that includes silicon, germanium, and carbon.

Abstract: A silicide bridged anti-fuse and a method of forming the anti-fuse are disclosed. The silicide bridged anti-fuse can be formed with a tungsten plug metalization process that does not require any additional process steps. As a result, anti-fuses can be added to an electrical circuit as trim elements for no additional cost.

Abstract: A silicon controlled rectifier, which has a substrate and an overlying epitaxial layer that is formed on the substrate, is formed in the epitaxial layer to have a number of semiconductor regions with alternating dopant conductivity types where a number of the regions extend through the epitaxial layer to the substrate.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming one or more trenches between the first and second regions, and implanting a dopant into the bottom surfaces of the trenches to form a continuous conductive path.

Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.

Abstract: In an electrically programmable non-volatile memory cell, the first terminal of a high density capacitive structure is electrically connected to a conductive structure to form a floating gate/first electrode, while the second terminal of the capacitive structure is used as a control gate, providing a cell with a high overall capacitive coupling ratio, a relatively small area, and a high voltage tolerance.

Abstract: A photonic crystal is formed on a semiconductor substrate using a semiconductor-based fabrication process by forming a number of alternating layers of material that have different dielectric constants. The layers of material are then etched to form a number of spaced-apart stacks of alternating layers of material. An interstack material is then formed between the stacks.

Abstract: A low-power bipolar transistor is formed to have an intrinsic emitter region with a sub-lithographic width, and an oxide layer that is self aligned to an overlying extrinsic emitter. The small extrinsic emitter region reduces the maximum current that can flow through the transistor, while the self-aligned oxide layer and extrinsic emitter reduces the base-to-emitter junction size and device performance variability across the wafer.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: A semiconductor integrated circuit with high Q inductors and capacitors is disclosed. A semiconductor electrical circuit is formed on a first die, while micro-electromechanical structures having inductance and capacitance are formed on a second die. The second die is attached and electrically connected to the first die as a flip chip.

Abstract: An ESD protection structure for use with bipolar or BiCMOS ICs that is relatively immune to thermal overheating and, thus, stable during an ESD event. This immunity is achieved by employing a heat sink region adjacent to a polysilicon emitter within a distance of less than 2 microns. Such a heat sink region provides temporal heat capacity to locally dissipate the heat generated during an ESD event. Bipolar transistor-based ESD protection structures according to the present invention include a semiconductor substrate and a bipolar transistor in and on the semiconductor. The bipolar transistor includes a base region, a collection region and a polysilicon emitter. The bipolar transistor-based ESD protection structures also include a heat sink region disposed above the semiconductor substrate adjacent to the polysilicon emitter.

Abstract: A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.

Abstract: The reduced signal-to-noise ratio of colored pixels that results from a lower conversion efficiency is eliminated by utilizing a programmable gain amplifier which individually applies a gain to the output of each colored pixel so that the maximum signal level of each colored pixel is matched to the maximum input range of an A/D converter.

Abstract: Drift in the reverse breakdown voltage of a surface zener diode is substantially reduced by forming a layer of material that includes titanium before or after the metallization steps that are used to form the first layer of metal (the metal-1 layer) or the second layer of metal (the metal-2 layer).

Abstract: The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer of epitaxial material. After this, a base material that includes silicon and germanium is blanket deposited, followed by the blanket deposition of a layer of protective material. The layer of protective material protects the base material from the chemical mechanical polishing step.

Abstract: A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact. The wafer is cut to form a plurality of dice, and the exposed edges of the dice are protected.