Abstract: The vertical diffusion of dopants from the gate and the bulk material into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and drain regions in a layer of composite material that includes silicon, germanium, and carbon.

Abstract: A dual-sided semiconductor device is formed on a wafer with a resistive element that is formed through the wafer. By forming the resistive element through the wafer, a resistive element, such as a large resistive element, can be formed on the wafer that requires very little silicon surface area.

Abstract: A low-power, synchronous pulse width modulator utilizes a first clock signal at a first frequency to generate a pulse-width modulated signal at the first frequency without requiring a second over sampling clock signal that has a substantially higher frequency by selecting taps from a phase shifting structure to synthesize the waveform.

Abstract: The efficiency of a heat exchanger is significantly improved by forming walls in an air flow structure, which has first grooves formed in the top surface of the structure and second grooves formed in the bottom surface of the structure, that block off alternating ends of the first and second grooves such that a first air source can only flow through the first grooves and a second air source can only flow through the second grooves.

Abstract: The power dissipation, logic complexity and chip area of a thermometer controller are all significantly reduced by utilizing a series of scan flip-flops that are connected together to form a bi-directional shift register, along with a gated clock signal that clocks the series of scan flip-flops.

Abstract: A semiconductor die is formed in a process that forms a trench opening in the semiconductor material prior to the formation of the contacts and the metal-1 layer. When contacts are then formed to contact circuit structures, such as a doped region in the top surface of the semiconductor material, a trench contact is formed that fills up the trench opening. During the final steps of the process, the back side of the semiconductor material is ground down to expose the trench contact. The wafer is cut to form a plurality of dice, and the exposed edges of the dice are protected.

Abstract: A single junction interdigitated photodiode utilizes a stack of alternating highly doped first regions of a first conductivity type and highly doped second regions of a second conductivity type, which are formed below and contact the first regions, to collect photons. In addition, a highly doped sinker of a first conductivity type contacts each first region, and a highly doped sinker of a second conductivity type contacts each second region.

Abstract: The loss of photogenerated electrons to surface electron-hole recombination sites is minimized by utilizing a first p-type surface region to form a depletion region that functions as a first barrier that repels photogenerated electrons from the surface recombination sites, and a second p-type surface region that provides a substantial change in the dopant concentration.

Abstract: The vertical diffusion of dopants from the gate into the channel region, and the lateral diffusion of dopants from the source and drain regions into the channel region resulting from thermal cycling during the fabrication of a MOS transistor is minimized by forming the source and drain regions in a layer of silicon germanium carbon.

Abstract: The rising edge triggered flip-flops and falling edge triggered flip-flops in one or more clock domains of a target system can be simultaneously initialized to predetermined logic states by activating the flip-flop set/clear inputs, freezing the flip-flop clock signals high or low, subsequently deactivating the flip-flop set/clear inputs, and then re-enabling the clock signals.

Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.

Abstract: The accuracy of the width measurement of a semiconductor resistor is improved by modifying the gate mask of a standard MOS transistor fabrication process to form an opening between regions of polysilicon that are used as a mask when the substrate or well material is implanted to form the resistor.

Abstract: Resistance and capacitance are added to a prototype die to fix or identify performance issues with the integrated circuit formed in the die by forming a thin piece of silicon on the top surface of the die. For resistance, vias are formed to regions on the metal traces and to opposite ends of the piece of silicon using a FIB system. For capacitance, a dielectric is formed on the piece of silicon, and a layer of metal is formed on the dielectric. Vias are formed to regions on the metal traces, to the piece of silicon, and to the layer of metal using the FIB system.

Abstract: The intrinsic base region of a bipolar transistor is formed to avoid a chemical interaction between the chemicals used in a chemical mechanical polishing step and the materials used to form the base region. The method includes the step of forming a trench in a layer of epitaxial material. After this, a base material that includes silicon and germanium is blanket deposited, followed by the blanket deposition of a layer of protective material. The layer of protective material protects the base material from the chemical mechanical polishing step.

Abstract: A communications system interleaves control pulses between the transitions in a serial bit stream to form an interleaved signal. The serial bit stream has a series of transitions and a series of gaps between transitions where a transition can not occur. An interleaver identifies gaps in the serial bit stream, and inserts the control pulses in the gaps to form the interleaved signal. The interleaved signal reduces the pin count when the interleaved signal is transmitted between chips.

Abstract: Thermal hot spots in the substrate of a semiconductor die, and the required surface area of the semiconductor die, are substantially reduced by forming thermal or thermal and electrical pipes in the substrate that extend from a bottom surface of the substrate to a point near the top surface of the substrate.

Abstract: The linear tuning range of a semiconductor varactor is substantially increased by forming a lightly-doped drain region of a first conductivity type in a semiconductor material of a second conductivity type between a heavily-doped diffusion of the second conductivity type and a lower-plate region of the semiconductor material.

Abstract: The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.

Abstract: An ESD protection structure includes a semiconductor substrate of a first conductivity type, and first and second well regions of a second conductivity type disposed in the substrate. The first and second well regions are separated by a gap region of the substrate. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The ESD protection structure also includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. The ESD protection structure also includes first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively.

Abstract: Access to a bus is granted to one of a number of requesting communication circuits that each submitted a bus control request during a request period of an arbitration period in response to the entries in a priority table. If a requesting communication circuit has an identity and priority that match the identity and priority of a communication circuit stored in a row of the priority table that corresponds with the arbitration period, access to the bus is granted to the requesting communication circuit.