Patents Represented by Attorney Mark C. Pickering

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  • Method of forming a dual damascene metal trace with reduced RF impedance resulting from the skin effect
    Patent number: 7223680
    Abstract: The RF impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fingers that extend away from the base region. When formed to have a number of loops, the metal trace forms an inductor with an increased Q.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: May 29, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Peter Johnson, Kyuwoon Hwang, Michael Mian, Robert Drury
  • BJT with ESD self protection
    Patent number: 7221036
    Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: May 22, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Yuri Mirgorodski
  • Next-generation network that reduces the effect of a service failure
    Patent number: 7218723
    Abstract: A next-generation network utilizes a three-tier, cascading fault approach to providing emergency stand-alone (ESA) switching in a circuit-to-packet (C2P) network. Calls that are placed to destination numbers which are connected to the same local network device are completed even when connectivity with a community network level has been interrupted, while calls that are placed to destination numbers which are connected to the same community are completed even when connectivity with a gateway media controller has been interrupted.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 15, 2007
    Assignee: Tellabs Petaluma, Inc.
    Inventors: T. Bryan Varble, Robert A. Bivin
  • Self-protecting transistor array
    Patent number: 7217966
    Abstract: A transistor array is self-protected from an electrostatic discharge (ESD) event which can cause localized ESD damage by integrating an ESD protection device into the transistor array. The ESD protection device operates as a transistor during normal operating conditions, and provides a low-resistance current path during an ESD event.
    Type: Grant
    Filed: February 18, 2005
    Date of Patent: May 15, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
  • Method of identifying state nodes at the transistor level in a sequential digital circuit using minimum combinatorial feedback loop
    Patent number: 7216307
    Abstract: The state nodes in a sequential digital circuit are identified by identifying the minimal combinatorial feedback loops that are present in the digital circuit. Each minimal combinatorial feedback loop has at least one driver node, and one driver node from each minimal combinatorial feedback loop is assigned to be the state node for the loop.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: May 8, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Tathagato Rai Dastidar, Amir Yashfe, Partha Ray
  • Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions
    Patent number: 7214992
    Abstract: The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than the width of the drain region, the current density in the drain region is significantly reduced which reduces the number of hot charge carriers that are trapped at the silicon-to-silicon dioxide interface which, turn in, reduces the drain breakdown voltage walk-in rate.
    Type: Grant
    Filed: October 27, 2004
    Date of Patent: May 8, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Andy Strachan, Douglas Brisbin
  • Laser powered integrated circuit
    Patent number: 7209503
    Abstract: An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: April 24, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
  • Closed-loop, supply-adjusted ROM memory circuit
    Patent number: 7206959
    Abstract: The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a memory to the next clock edge to determine a timing value. When the clock frequency changes from a first frequency to a second frequency, the timing value changes from a first value to a second value. The magnitude of the supply voltage is changed to return the timing value to the first value.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: April 17, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Wai Cheong Chan, James Thomas Doyle, Pavel Poplevine, Murali Krishna Varadarajula, Hsing-Chien Roy Liu, Gordon Mortensen
  • Tamper-proof latch cover
    Patent number: 7204105
    Abstract: A latch in a door is protected from an unauthorized entry by forming a first bracket that fits around the latch, and a second bracket that is rotatably connected to the first latch. The second bracket covers the latch when rotated to be in a first position, and exposes the latch when rotated to be in a second position.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 17, 2007
    Assignee: Tellabs Petaluma, Inc.
    Inventors: James Edward Hooper, G. James Keller
  • Method and apparatus of adding grant information to a memory
    Patent number: 7200732
    Abstract: A scrambling operation is used to space apart the grants that a communication circuit receives during a period of time, such as 512 arbitration periods. An operator can enter the number of arbitration periods that a communication circuit is to receive in blocks of sequential logical address ranges. The logical addresses are then changed to physical addresses that are spaced apart, thereby significantly reducing the buffering required by the communication circuit.
    Type: Grant
    Filed: January 23, 2004
    Date of Patent: April 3, 2007
    Assignee: Tellabs Petaluma, Inc.
    Inventors: Paul Brian Ripy, Keith Quoc Chung, Gary J. Geerdes, Christophe Pierre Leroy
  • Semiconductor sensor device using MEMS technology
    Patent number: 7192819
    Abstract: A semiconductor sensor device is formed using MEMS technology by placing a thin layer of single-crystal silicon, which includes semiconductor devices, over a cavity, which has been formed in a semiconductor material. The thin layer of single-crystal silicon can be formed by forming the semiconductor devices in the top surface of a single-crystal silicon wafer, thinning the silicon wafer to a desired thickness, and then dicing the thinned wafer to form silicon layers of a desired size. The MEMS device can be used to implement a pressure sensor, microphone, temperature sensor, and a joystick.
    Type: Grant
    Filed: July 20, 2004
    Date of Patent: March 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Gobi R. Padmanabhan, Visvamohan Yegnashankaran
  • Method of forming a semiconductor structure with non-uniform metal widths
    Patent number: 7192857
    Abstract: A power transistor structure uses metal drain and source strips with non-uniform widths to reduce variations in current density across the power transistor structure. The reductions in current density, in turn, reduce the source-to-drain turn on resistance and maximize the overall current carrying capacity of power transistor structure.
    Type: Grant
    Filed: April 20, 2005
    Date of Patent: March 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Andy Strachan
  • High speed, universal polarity full adder which consumes minimal power and minimal area
    Patent number: 7185042
    Abstract: A low power, high speed full adder cell is described. This cell supports all possible combinations of active high/active low input/output signal polarity (32 different combinations), without adding extra inverters or extra transistors. The cell makes liberal use of complementary metal oxide semiconductor (CMOS) transmission gates in order to minimize the number of transistors used, and to minimize their stacking. This significantly decreases the total transistor gate area consumed, resulting in minimal power dissipation and minimal cell size.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: February 27, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Ronald Pasqualini
  • Laser powered clock circuit with a substantially reduced clock skew
    Patent number: 7180379
    Abstract: A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.
    Type: Grant
    Filed: May 3, 2004
    Date of Patent: February 20, 2007
    Assignee: National Semiconductor Corporation
    Inventors: Peter J. Hopper, Philipp Lindorfer, Vladislav Vashchenko, Yuri Mirgorodski
  • Electronics card with an alignment opening
    Patent number: 7170755
    Abstract: An electronics card, such as a backplane, is precisely aligned with a structure, such as a card cage, via alignment tabs by forming the electronics card to have alignment openings that extend through the electronics card and snuggly accept the tabs. The alignment opening has a width, while the tabs have a thickness that is greater than zero and less than the width. Further, the alignment openings have lengths that are the same size as the lengths of the alignment tabs.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: January 30, 2007
    Assignee: Tellabs Petaluma, Inc.
    Inventor: G. James Keller
  • Depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
    Patent number: 7161216
    Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
    Type: Grant
    Filed: October 22, 2003
    Date of Patent: January 9, 2007
    Assignee: National Semiconductor Corporation
    Inventor: Terry Lines
  • Completely isolated synchronous boost DC-to-DC switching regulator
    Patent number: 7148668
    Abstract: The leakage current due to a parasitic PNP bipolar transistor in the PMOS switching transistor of a synchronous boost DC-to-DC switching regulator is substantially eliminated by placing the input voltage on the body of the PMOS switching transistor when the input voltage is greater than the output voltage, and placing the output voltage on the body of the PMOS switching transistor when the input voltage is less than the output voltage.
    Type: Grant
    Filed: April 28, 2004
    Date of Patent: December 12, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Michael John Collins
  • Method for forming a depletion-mode transistor that eliminates the need to separately set the threshold voltage of the depletion-mode transistor
    Patent number: 7144795
    Abstract: A semiconductor circuit with a depletion-mode transistor is formed with a method that eliminates the need for a separate mask and implant step to set the threshold voltage of the depletion-mode transistor. As a result, the method of the present invention reduces the cost and complexity associated with the fabrication of a semiconductor circuit that includes a depletion-mode transistor.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: December 5, 2006
    Assignee: National Semiconductor Corporation
    Inventor: Terry Lines
  • Silicon controlled rectifier structures with reduced turn on times
    Patent number: 7126168
    Abstract: The turn on time of an electrostatic discharge (ESD) structure, such as a silicon controlled rectifier (SCR), a low-voltage triggering SCR (LVTSCR), and a bipolar SCR (BSCR), is reduced by turning on the structure in two steps: a first step that locally turns on the pnp and npn transistors, and a second step that, over time, fully turns on the structure.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: October 24, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper
  • Method of forming a conductive structure
    Patent number: 7118998
    Abstract: A conductive structure provides a conductive path from a first region in a semiconductor material to a second spaced apart region in the semiconductor material by forming a plurality of trenches between the first and second regions, implanting a dopant into the bottom surfaces of the trenches, and then annealing the wafer to cause the dopant at the bottom surfaces to diffuse and form a continuous conductive path.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 10, 2006
    Assignee: National Semiconductor Corporation
    Inventors: Charles A. Dark, William M. Coppock