Abstract: Spacers are formed having widths that vary as a function of the spacing between the mandrels upon which the conformal material that defines the spacers is deposited and etched. As the spacing between adjacent mandrels decreases, the width of the resulting spacers decreases. The correlation between mandrel spacing and sidewall structure width is independent of the thickness of the conformal material as-deposited. As the spacing between the mandrels decreases, the decrease in width becomes more pronounced, particularly at mandrel spacings of five microns or less. Thus, by making adjacent mandrels closer together or further apart and adjusting mandrel height, active/passive components having differing widths/lengths may be formed from the same conformal layer.

Abstract: A coaxial wiring structure that is constructed by depositing and etching a series of conductor layers and insulator layers.

Abstract: A method of reproducing sub-micron images in a first imaging layer. A second imaging layer is deposited on an etch-stop film formed on the first layer, and the second imaging layer is exposed to an E-beam at low dose. The resulting standing wave exposure pattern is converted into a corresponding topology pattern having peaks and valleys by exposure to a wet developer. Ions are implanted through the second imaging layer into portions of the first imaging layer below the valley portions of the standing wave topology pattern. The second imaging layer is removed without appreciably attacking the etch-stop layer, and then the etch stop layer is removed without appreciably attacking the first imaging layer. The first imaging layer is anisotropically etched in an O.sub.2 RIE, the implanted regions serving as an etch mask. The process results in the formation of small images at high throughput.

Abstract: A method of forming a conductive structure on a substrate by using both of the via-filling and stud-forming metallization techniques. A stud that is approximately one-half the thickness of the final stud is defined on a conductive layer. The stud-forming mask is left in place. Then the sidewalls of the mask are positively tapered, and an insulator layer is deposited on the substrate. The insulator is then etched to expose the stud forming mask, and the mask is removed. The sidewalls of the vias thus defined in the insulator layer are then positively tapered. By positively tapering both the stud mask prior to insulator deposition and the insulator via prior to metal deposition, insulator gap-fill and metal hole-fill problems are eliminated.

Abstract: A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H.sub.3 PO.sub.4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

Abstract: A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode which has dual control gates disposed thereon. Each control gate includes a layer of dual electron injector structure (DEIS) and a polysilicon gate. When writing a "0" from the volatile storage capacitor to the floating gate, one of the control gates removes charge from the floating gate. To write a "1", the other control gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic state and the logic state to be written in are identical. In order to minimize the adverse effects of process variations, the gate electrode of the word line device is electrically in common with one of the control gates.

Abstract: A process for forming deep (>6.mu.m) trenches in a silicon substrate. The substrate is etched through a silicon oxide mask in a plasma having 75%-86% HCl, 9%-16% O.sub.2, and 1%-8% BCl.sub.3. The resulting trenches have substantially vertical sidewalls and rounded bottom surfaces. The plasma etch is performed at high power and low pressure, so that it achieves a high aspect ratio at a minimum etch bias.

Abstract: A charge pumping structure is disclosed for use in a substrate bias voltage generator. It includes a capacitor on a substrate region for coupling to a first node periodic voltage signals received at a second node. A first diode structure provides a current path from the first node to the substrate and a second diode structure provides a current path between the first node and a reference potential, which is typically the ground. The first diode structure includes a PN junction diode, an isolation ring for collecting minority charge carriers injected into the substrate and is constructed on a portion of the substrate that has a lower doping concentration than the underlying substrate portion establishing a built-in electric field which inhibits the flow of minority carriers from the first diode to the underlying substrate.

Abstract: A non-volatile dynamic memory cell in which the non-volatile element has two different areas for electron injection, such that direct overwriting of previously stored non-volatile data is permitted without an intervening erase cycle. The non-volatile storage element is a floating gate electrode which has dual control gates disposed thereon. Each control gate includes a layer of dual electron injector structure (DEIS) and a polysilicon gate. When writing a "0" from the volatile storage capacitor to the floating gate, one of the programming gates removes charge from the floating gate. To write a "1", the other programming gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.

Abstract: A method of enhancing first order alignment marks formed in the respective layers of a processed semiconductor wafer in which critical masking steps are carried out. After a given mark is formed, it is tested for visual contrast. If the contrast is insufficient to provide adequate alignment, a block mask is formed on the critical mask. The block mask exposes all of the alignment target areas and protects the product regions of the wafer, and the critical mask only exposes the mark to be enhanced. The mark is then etched for a time period which is a function of the measured visual contrast. This method of selectively enhancing selected ones of the first order alignment marks greatly enhances the utility of such marks, increasing the accuracy of critical masking steps.

Abstract: An oxygen-impervious pad structure which reduces the bird's beak profiles in semi-recessed oxide isolation regions. The sidewalls of a conventional silicon oxide - silicon nitride pad are coated with a thick layer of oxynitride. A thin layer of oxynitride is grown on the substrate surface prior to deposition of the thick oxynitride layer. The thick oxynitride layer prevents lateral oxidizing specie diffusion through the oxide layer of the conventional pad, and the thin oxynitride layer prevents lateral oxidizing specie diffusion through the pad-substrate interface into the substrate region beneath the pad.

Abstract: Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD.

Abstract: A method of selectively tailoring the slope of via hole sidewalls. A first polyimide layer (in which the vias are to be formed) is covered by a strippable layer, and the two layers are isotropically etched. By varying the thickness of the strippable layer with respect to that of the polyimide layer, the slope of the via hole sidewalls can be controlled.

Abstract: A contact structure suitable for use in a CMOS device to prevent or suppress the latch-up phenomenon in the device. It uses two degeneratively doped regions of different conductivity type with a tunnel injecting interface therebetween and a conductive segment contiguous to one of the two regions. Using such a structure as the source of an FET in a CMOS arrangement causes the emitter area and the base spreading resistance of the corresponding parasitic bipolar transistor to be reduced. This in turn causes the current gain of the parasitic transistor to decrease and the latch-up phenomenon to be prevented or suppressed.

Abstract: A test site for gauging the adhesion between the insulating layers and the metal layers used to produce the various devices on a semiconductor chip. The chip-sized test site can be formed along with the product chips on the product wafers. The layers of the test site are arranged such that a first polyimide layer forms a first test interface with a silicon nitride layer and a second test interface with a first metal layer, and a second polyimide layer forms a third test interface with a second metal layer, a fourth test interface with the first polyimide layer, and a fifth test interface with the silicon nitride layer. These five interfaces form a single continuous adhesion test interface. During a 90.degree. peel test, the layers of the test site will sequentially separate along this interface. Thus, the adhesion at five different interfaces can be tested during a single peel test on a chip-sized test site.

Abstract: A lift-off metal deposition process in which a high temperature polyimide layer (i.e. a polyimide having a high imidization temperature) is applied to a first polyimide layer. The two layers are anisotropically etched through a photoresist mask to form vias in the first polyimide layer. After application of a metal layer, the high-temperature polyimide layer is lifted off the first polyimide layer, which remains as a passivation layer.

Abstract: A substrate for packaging semiconductor chips is provided which is structured with conductors having opposite ends terminating in a mounting surface and intermediate portions extending beneath the surface. The ends of the conductors are arranged in repeating patterns longitudinally along the substrate separated by orthogonal strips free of conductor ends to allow for dense surface wiring. The repeating patterns are arranged to allow for chip mounting sites having sufficient spacing to allow for surface wiring. In this way chips in the same and repeat pattern can be connected by personalized surface wiring and preset substrate conductors.

Abstract: A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

Abstract: A process is provided for making semiconductor structures, such as CMOS structures, which includes forming on a surface of a semiconductor body a layer from a material which is impervious to oxygen diffusion therethrough and patterning this layer to define the position of both the active and field isolation regions by partially removing this layer from the areas where the field isolation regions are to be formed. This oxygen impervious layer may be a dual dielectric structure consisting of a layer of silicon dioxide adjoining the semiconductor body and a layer of silicon nitride adjoining the silicon dioxide. The resulting structure includes an oxygen impervious layer which is used both for protecting all underlying oxidizing regions from oxidation and for defining the position of the active regions of the structure.

Abstract: A method of making an aperture of a predetermined shape into a dielectric substrate which will lockingly receive a deformable contact pin. It includes providing a dielectric material which shrinks in response to a heat treatment by an amount which is different in one direction from that in another direction, and which irreversibly changes dimensions in its two orthogonal directions in proportion to this difference. An aperture is formed in such a material, in a direction normal to the plane of the two orthogonal directions and the material is subjected to a heat treatment that causes a differential shrinkage in the aperture and a change in the shape of the aperture. A deformable contact pin is then forced into a locking position in the aperture.