Abstract: In scan testing of logic parts, this invention provides an inexpensive transition fault test by changing the sequence of application of the A/C and B clocks. In each machine test cycle the B clock is triggered first, and the A/C clock is triggered second. The periodicity of the clocks is not changed for a particular cycle, because in one cycle the B-to-A/C clocking that naturally occurs provides a minimum test window TP for performance and transition fault testing. Thus, less sophisticated scan test equipment can now provide both transition fault and stuck fault testing, without an increase in complexity or expense.

Abstract: A method of forming a bridge contact between a source diffusion region of a transfer gate FET and a polysilicon-filled trench storage capacitor electrodes of the FET. A layer of titanium is evaporated at a temperature of approximately 370.degree. C., so that the titanium has a substantially columnar grain structure and a minimum of matrix material. The bottom portions of the columnar grains have a lateral length that approximates the lateral length of the dielectric separating the source diffusion from the poly-filled trench. Thus, upon sintering at 700.degree. C. in an N.sub.2 atmosphere, titanium silicide will form over all exposed silicon regions as well as the dielectric, without shorting the FET electrodes together.

Abstract: A structure and method for selectively forming interconnections between the interconnect lines of a printed circuit board. At the same time solder is deposited through a solder application mask to bond the modules to the board, solder is also deposited on pad interconnect structures between the interconnect lines. Thus, line interconnections can be formed at minimal additional cost, reducing the number of different boards needed to mount different sets of modules or alternate component or circuit configurations. In a preferred embodiment, the pads comprise an arcuate member and an elongated member extending within the arc described by the arcuate member. By optimizing the spacing between the members, the total area of the members, and the volume of the solder, a highly reliable solder fillet interconnection can be formed.

Abstract: A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

Abstract: A logic synthesis network for efficiently combining respective bit pairs of first and second operands to produce respective sum bits and a carry bit associated with the most significant sum bit. A dummy generator receives the respective bit pairs and generates first and second dummy sum signals, and first and second pairs of dummy carry signals. A first dummy selector chain selects the appropriate dummy sum and carry signals of all the bits other than the least significant bit, as a function of the state of the first pair of dummy carry signals generated for the least significant bit pair. A second dummy select chain selects the appropriate dummy sum and carry signals for all the bit pairs other than the least significant bit pair, as a function of the state of the second pair of dummy carry signals generated for the least significant bit pair.

Abstract: A method of forming a plurality of conductive studs within a non-planar insulator layer (e.g., PSG or BPSG) disposed between a first series of conductive structures arranged on a substrate and metal lines formed on the upper surface of the insulator layer. Vertical vias are defined through the insulator layer to expose at least one of the first conductive structures on the substrate. A conformal metal layer (e.g., CVD W) is deposited on the insulator layer to fill the vias. Then, the metal layer and the insulator layer subjected to a polish etch in the presence of an abrasive slurry, to remove portions of the metal layer outside of the vias while simultaneously planarizing the insulator layer.

Abstract: A sub-surface interconnection structure for coupling an n-type diffusion to a p-type diffusion. The structure is a conductor-filled trench disposed between the diffusion regions. The trench has a thin dielectric layer on its sidewalls and bottom. The conductor within the trench contacts the diffusion regions. Parasitic device formation between the diffusion regions is suppressed because the trench provides a parasitic gate that is shorted to the parasitic source regions (i.e., the coupled diffusion regions). Moreover, the trench provides an enlarged contact to the coupled diffusion regions for the subsequently-applied metal layer.

Abstract: For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other.

Abstract: A method for forming a silicide bridge bewteen a diffusion region and an adjacent poly-filled trench separated by a thin dielectric. Silicon is selectively grown over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth over other insulator regions. A refractory metal layer is then deposited and sintered under conditions that limit lateral silicide growth, forming the bridge. This process avoids the random fails produced by previous processes while enhancing the compatibility of bridge formation with shallow junctions, without introducing extra masking steps or other process complexities.

Abstract: A non-volatile storage cell comprising a field effect transistor having source, gate, and drain electrodes. The gate electrode includes a gate stack having a dielectric layer, a charge storage structure comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means. A control electrode is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

Abstract: A method for fabricating a semiconductor integrated circuit structure having a submicrometer length device element is described wherein a surface isolation pattern is formed in a semiconductor substrate to define regions which are designated to contain devices. A first insulating compound layer is formed on the surface of the semiconductor substrate which is designated to be in part the gate dielectric. Subsequently, a polycrystalline silicon layer is deposited onto the compound layer. The polycrystalline silicon layer is heavily doped by phosphorus ion implantation and annealed below about 850.degree. C. Polycrystalline silicon portions are delineated by photolithography and dry etching. Dry etching is carried out in SF.sub.6 -Cl.sub.2 /He at a low power density of about 0.1 to 0.3 watts/cm.sup.2. The remaining portions of polycrystalline silicon layer are subjected to a thermal oxidation at a temperature of about 800.degree. C.

Abstract: In an optical storage system where an information bearing surface moves relative to a read/write head the latter includes a transparent body in which light beams sent to and from the surface are guided by multiple internal reflections. Beam shaping and focussing is effected by optical elements integrated in the surface of the body at the locations where the internal reflections occur. A distortion free imaging system is obtained with two series-arranged aspheric reflection surfaces which focus the beam on the information bearing surface. The separation of the input and the reflected beam paths is achieved with a polarizing beam splitter and an associated quarter-wave layer. For readout of a magneto-optic information bearing surface a nonperfect polarizing beam splitter is used in connection with a differential detection scheme to increase the signal to noise/ratio.

Abstract: A conformal organic layer is used to define spacers on the sidewalls of an organic mandrel. The organic layer (e.g., parylene) can be deposited at low temperatures, and as such is compatible with temperature-sensitive mandrel materials that reflow at high deposition temperatures. The conformal organic material can be dry etched as the same rate as the organic mandrels, while being resistant to wet strip solvents that remove the organic mandrels. This series of etch characteristics make the organic mandrel-organic spacer combination compatible with a host of masking applications.

Abstract: A plasma comprised of a fluorinated gas, an oxidant, and up to 15%-20% chlorofluorocarbon gas etches non-insulating materials such as tungsten and silicon at very high etch rates while providing enhanced etch rate ratios to photoresist and insulators.

Abstract: A plasma comprised of trifluorochloromethane and an oxidant etches non-insulating materials such as tungsten at very high etch rates when the oxidant comprises at least 50% of the plasma by volume.

Abstract: A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder. The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide and is a bridge contact that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.

Abstract: A method for the digital slope control of the output signals of power amplifiers, as well as a power amplifier suitable for carrying out the method as described. One way of representing the actual slope value is via the number of clock pulses applied to a counter during a measuring interval which depends in its duration on the slope. Such a measuring interval is produced by applying the pulses of a ring oscillator containing one of the power amplifiers to another counter until the overflow of the latter. Another mode of representing the actual slope value consists in counting the number of pulses of the ring oscillator during a measuring interval of predetermined duration. Actual and nominal values of the slope are compared. The results of this comparison change the contents of a left/right-shift register.

Abstract: A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit.

Abstract: A method for anisotropically etching a thick tungsten layer atop a thin underlayer comprised of titanium nitride, by exposure to a gaseous plasma comprised of a binary mixture of chlorine gas and oxygen, wherein oxygen comprises approximately 25%-45% of the mixture by volume. This plasma provides a combination of high tungsten etch rate, highly uniform etching, anisotropic profiles, and high etch rate ratio to underlaying glass passivation layers.

Abstract: A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder. The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide and is a bridge contact that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.