Patents Represented by Attorney, Agent or Law Firm Mark F. Chadurjian
  • Patent number: 4568631
    Abstract: An optical photolithographic process in which resist lines having widths in the micron and sub-micron range are produced without the use of a fine line photomask. A positive photoresist having an additive for image reversal is applied to the surface of a semiconductor substrate. The photoresist is exposed through a photomask to ultraviolet light. The edges of the opaque sections of the mask diffract the ultraviolet light, forming partially exposed areas between the exposed and unexposed areas formed in the photoresist. After development in a solvent to remove the exposed areas, the photoresist undergoes an image reversal process. The photoresist is first baked at 100.degree. C. for 30 minutes. During this bake step, the photoactive decomposition products present in the partially exposed areas react, freezing the solubility of the partially exposed areas with respect to that of the unexposed areas.
    Type: Grant
    Filed: April 30, 1984
    Date of Patent: February 4, 1986
    Assignee: International Business Machines Corporation
    Inventors: Dinesh A. Badami, Mark C. Hakey, Holger Moritz
  • Patent number: 4566173
    Abstract: The method in accordance with the invention is used for the production of field-effect transistors and preferably implemented in such a manner that a thin aluminum layer (2) is deposited on the surface of a silicon substrate (1), for example, by means of a basic cleaning solution containing aluminum, that subsequently thermal oxidation is effected, during which, in addition to a silicon dioxide layer (3), an about 1 to 1.5 nm thick layer (4) containing aluminum oxide and silicon dioxide is formed and that finally, if required, at least one further layer, for example, an Si.sub.3 N.sub.4 (5) or an Si.sub.3 N.sub.4 (5) and an SiO.sub.2 layer are deposited. By adding about 400 ppb aluminum to the cleaning solution, which in the finished structure equals a quantity of aluminum of about 250 pg/cm.sup.2 layer surface, the threshold voltage V.sub.S is raised by about 470 millivolts.
    Type: Grant
    Filed: June 4, 1982
    Date of Patent: January 28, 1986
    Assignee: International Business Machines Corporation
    Inventors: Werner Gossler, Anneliese Strube, Manfred Zurheide
  • Patent number: 4542950
    Abstract: A ZIF connector block for establishing an electrical connection between the I/O pads of an edge-connected printed circuit board and a set of printed conductors. The connector has two opposing rows of contacts. The contacts are of two different lengths, both adjacent and opposite ones of the contacts having different lengths. An upper housing has a plurality of cams mounted thereon, each cam having a different cam surface profile. The surface profiles of the cams are staggered into two different lengths corresponding to the lengths of the contacts so that when the cams are actuated by imparting a vertical motion to the upper housing, the contacts will simultaneously engage the I/O pads in a staggered fashion. Moreover, the surface profiles of the cams are constructed so that after simultaneous engagement, the contacts perform sequential wipe cycles on the pads. The staggered and sequential wipe cycles promote the stability of the board within the connector without sacrificing electrical integrity.
    Type: Grant
    Filed: February 21, 1984
    Date of Patent: September 24, 1985
    Assignee: International Business Machines Corporation
    Inventors: John B. Gillett, John A. Miraglia
  • Patent number: 4532700
    Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.
    Type: Grant
    Filed: April 27, 1984
    Date of Patent: August 6, 1985
    Assignee: International Business Machines Corporation
    Inventors: Wayne I. Kinney, Jerome B. Lasky, Larry A. Nesbit
  • Patent number: 4527325
    Abstract: A process is provided for fabricating a semiconductor structure wherein the structure has to be exposed to certain oxidizing conditions during certain of its processing steps, such as its high temperature annealing in an oxidizing ambient. It includes depositing a "sacrificial" layer, such as silicon, to provide a uniformly oxidizing surface during subsequent annealing operations. This sacrificial layer, which oxidizes uniformly, produces an oxide layer which also etches uniformly. Thus, after the annealing is completed, the surface oxide is removed through etching and the sacrificial layer is then also removed through a different etching step.
    Type: Grant
    Filed: December 23, 1983
    Date of Patent: July 9, 1985
    Assignee: International Business Machines Corporation
    Inventors: Henry J. Geipel, Jr., Charles A. Schaefer, Francis R. White, John M. Wursthorn
  • Patent number: 4442503
    Abstract: A device for storing and displaying graphic information having a storage unit for storing both blocks and rows of data and retrieving rows of data. The storage unit consists of two storage segments, with eight storage modules each, which can operate in an interleaved mode. This permits two-dimensional addressing which consists of distributing the individual elements of a data block over the various separately addressable modules of the storage unit so that no one module contains more than one element of the data block, and that all elements of the data block can be read out in one cycle through simultaneous access of all of the storage modules.
    Type: Grant
    Filed: April 16, 1981
    Date of Patent: April 10, 1984
    Assignee: International Business Machines Corporation
    Inventors: Dieter Schutt, Manfred Schwengler, Hartmut Ulland, Helmut H. Weis
  • Patent number: D277580
    Type: Grant
    Filed: November 16, 1981
    Date of Patent: February 12, 1985
    Assignee: International Business Machines Corporation
    Inventor: John A. Wiseman
  • Patent number: D284375
    Type: Grant
    Filed: March 19, 1984
    Date of Patent: June 24, 1986
    Assignee: International Business Machines Corporation
    Inventors: Joseph G. Bullock, David M. Gresham, Ted F. Kelley, Leroy H. Moser, Kenneth L. White, Philip C. Yenerich, Roland Zapfe, Kurt W. Gibson