Abstract: A dynamic random access memory (DRAM) of 2/3 VDD precharge scheme is disclosed. A latch driving circuit controls the voltage of the common node of a sense latch so as to limit the downward voltage swing of bitlines to 1/3 VDD, a low level restore voltage. The sense latch is coupled to a pair of I/O data lines through PMOS FET column switches. This invention provides high speed memory operation and reduces power consumption.

Abstract: A process for sputter deposition wherein high aspect ratio apertures are coated with conductive films exhibiting low bulk resistivity, low impurity concentrations, and regular morphologies. A collimator is used having an aspect ratio that approximates the aspect ratio of the apertures.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A redundancy system formed on a semiconductor chip is provided which includes circuits for testing a memory array to locate a faulty element therein, a register for storing an address of the faulty element and electrical fuses blown in response to binary digits of the address stored in the register upon application of an enable signal from a single input to the semiconductor chip. The enable signal passes through logic circuits on the chip such that the fuses cannot be programmed or blown unless the enable signal is present. An address decoder coupled to outputs from the fuses substitutes a redundant element for the faulty element.

Abstract: A structure and method for selectively forming interconnections between the interconnect lines of a printed circuit board. At the same time solder is deposited through a solder application mask to bond the modules to the board, solder is also deposited on pad interconnect structures between the interconnect lines. Thus, line interconnections can be formed at minimal additional cost, reducing the number of different boards needed to mount different sets of modules or alternate component or circuit configurations. In a preferred embodiment, the pads comprise an arcuate member and an elongated member extending within the arc described by the arcuate member. By optimizing the spacing between the members, the total area of the members, and the volume of the solder, a highly reliable solder fillet interconnection can be formed.

Abstract: An interlocked on-chip ECC system for DRAMs wherein performance degradations due to on-chip ECC are minimized without compromising accurate ECC operations. Several interlocks used in the system insure that the data thereto is valid at certain critical stages. The remainder of the system is allowed to run on a self-timed basis to maximize speed. For example, a dummy data line is used to signal the ECC when data from the DRAM arrays is valid during a fetch operation; the same dummy data line also signals the DRAM arrays when the data from the ECC is valid during a write-back operation.

Abstract: A signal margin testing system is provided for a memory having a word line voltage boosting circuit which uses a test mode decode circuit to selectively disable the word line boosting circuit and then read out data from storage cells in the memory.

Abstract: An integrated boost and local word line drive system that enhances the speed of the word line drive without providing excessive voltage stresses to the driver devices. A charge reservoir stores a boost voltage under the control of a charge pump that is regulated by a voltage regulator. One of the local word lines coupled to a selected master word line is enabled by a driver that receives the boost voltage. The switching times and signal slew rates of the driver, as well as the boost voltage, are controlled to prevent excessive gate stresses in the support circuitry.

Abstract: An improved contactless temperature measurement system is provided which includes a workpiece, a chamber containing the workpiece with the walls thereof being substantially transmissive to radiation at wavelengths other than a given wavelength and substantially reflective at the given wavelength to remove the dependence of the apparent or measured temperature on the workpiece emissivity variations or fluctuations.

Abstract: A voltage reference circuit that produces an output offset from a supply voltage by approximately two volts, the output being relatively stable in the face of vacillations in the external power supplies. The first leg of the circuit utilizes devices having differing Vt's to produce an internal reference of one volt below Vdd. In a first embodiment of the invention, the second leg has a first device that is diode connected, wherein the gate receives the internal reference and the source is at the high power supply, and a second high Vt diode connected device. The two devices are matched to have the same overdrive current, which is at a voltage that is a function of the difference between the gate-to-source voltage of the first device and the threshold voltage of the first device. Thus, the output is a function of the overdrive to, and the diode drop across, the second high-Vt device.

Abstract: In a memory addressable by row and by column and operable in page mode whereby multiple column cycles are performed within a single row cycle, an arrangement is provided for stepping the row address for selected column cycles whereby sustained page mode operation can be provided throughout memory address space. Preferably, stepping occurs in response to a row change signal supplied when a column address strobe becomes active and the direction of stepping is determined by a mode signal supplied when a row address strobe becomes active. Memory segmentation is employed to facilitate simultaneous activation and restoring of multiple rows.

Abstract: A non-volatile memory cell uses two different areas for electron injection, allowing direct overwriting of previously stored data without an intervening erase cycle. A floating gate FET has dual programming gates disposed on its floating gate. Each programming gate includes a layer of dual electron injector structure (DEIS) and a polysilicon electrode. When writing a "0", one of the programming gates removes charge from the floating gate. When writing a "1", the other programming gate injects charge into the floating gate. The above charge transfer does not take place if the previously stored logic gate and the logic state to be written in are identical.

Abstract: A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.

Abstract: In computer systems deliberate initializations/resets of the processor latches which represent the internal processor states are necessary to erase only such information which is not required for a subsequent operation, e.g., processing/logging error data, prior to a processor start. One or more reset areas are defined which are initialized/reset in a staggered mode, where in each area a group of latches is assembled which have to be initialized/reset depending on the cause, e.g., power-on, for such a system initialization/reset. The latches within a reset area are connected to form shift registers which are initialized/reset by propagating a binary zero through all latches of the area(s) to be reset.

Abstract: A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW.

Abstract: A Video Random Access Memory device wherein full and efficient use of a serial access memory portion provides a simple and efficient means of avoiding Mid-Line Reloads. Selected parts of two different rows in a random access memory portion are transferred simultaneously to the serial access memory portion via addressable transfer gates under the control of address/control logic.

Abstract: A memory system in which access to faulty memory blocks is prevented. A test is carried out to see if there are enough functional memory blocks to store a given amount of information. If not, an address mode signal is generated that interchanges the row/column accesses for a given multi-bit address word, such that a line fault is isolated to only one memory block. This reconfigures the system to maximize available memory space without adding excessive access delays.

Abstract: A BiCMOS output driver in which a bipolar device is driven by a control signal that biases the collector of an NFET. The control signal enables the bipolar to pull an output node to full potential (ground) quickly. The signal then falls within one nanosecond after the output reaches ground, pulling the bipolar out of saturation. A separate feedback device coupled between the base of the bipolar and ground can be added to pull the bipolar out of saturation before the control signal falls.

Abstract: A method and semiconductor structure are provided for intermixing circuits of two or more different cell classes, such as standard cells and gate array cells, on a common chip or substrate with minimum gound rule separation between adjacent cells of different classes. Cell locations are defined with given boundaries and contiguously arranged on the surface of a semiconductor chip, and then either standard cell type or gate array type circuits are formed within any of the cell locations to provide a structure for balancing chip density and performance versus hardware turn-around-time.

Abstract: A memory is provided which includes a semiconductor substrate having a major surface and a trench disposed therein having a longitudinal axis, storage means disposed on a given sidewall of the trench, switching means having a control element and a current carrying element disposed on the given sidewall of the trench between the storage means and the major surface of the substrate and coupled to the storage means, a first electrically conductive line disposed on the given sidewall in contact with the control element of the switching means and having a longitudinal axis arranged parallel to the longitudinal axis of the trench, and a second electrically conductive line disposed on the major surface of the semiconductor substrate in contact with the current carrying electrode of the switching means and having a longitudinal axis arranged orthogonal to the longitudinal axis of the trench.