Patents Represented by Attorney Martine, Penilla & Gencarella, LLP
  • Patent number: 7922866
    Abstract: Positional relationships are established in a process chamber. A base is configured with a lower electrode surface to support a wafer, and an upper electrode has a lower surface. A drive mounted on the base has a linkage connected to the upper electrode. A fixture placed on the lower surface moves into a desired orientation of the lower electrode. With the upper electrode loosely connected by the linkage to the drive, the fixture transfers the desired orientation to the upper electrode. The linkage is tightened to maintain the desired orientation, the fixture is removed and a process exclusion insert is mounted to the upper electrode. The drive moves the upper electrode and the insert to define an inactive process zone between the upper electrode and the wafer on the lower electrode to protect a central area of the wafer during etching of a wafer edge environ around the central area.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: April 12, 2011
    Assignee: Lam Research Corporation
    Inventors: Gregory S. Sexton, Andrew D. Bailey, III, Alan M. Schoepp, John D. Boniface
  • Patent number: 7924472
    Abstract: This invention relates to the updating of image processing control data that is related to image data and controls image processing of the image data. An image related data generator generates an image file that includes image data and image processing data pre-stored therein. The image processing control data can be updated according to the following process. The image related data generator sends specification data that specifies image processing control data to be updated to an update data server. Then the image related data generator receives the update data from the update data server. And the image related generator updates the image processing control data stored therein with the update data.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: April 12, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Yasumasa Nakajima
  • Patent number: 7924468
    Abstract: The device employs a plurality of coefficients recorded in image data to detect whether edges are included per block, and determines as the blur level the proportion of edges, among the detected edges, in which the edge width is over a certain threshold. The device also determines, per block, coordinates composed of a first coefficient value representing frequency components in a first direction in the blocks and a second coefficient value representing frequency components in a second direction perpendicular to the first direction, and calculates the extent of bias in the distribution of the coordinates as the ellipticity. The device determines whether or not blurring has been produced by camera shake in an image based on the relationship between the blur level and ellipticity which have thus been determined.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: April 12, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Kimitake Mizobe
  • Patent number: 7925952
    Abstract: A method for testing functionality on a JAVA enabled device is provided. The method includes downloading a test to the JAVA enabled device from a management unit having access to the test. The management unit is connected with a partner device polling the management unit. A message is forwarded from the JAVA enabled device to the partner device through the management unit. The expected content of the message is forwarded from the JAVA enabled device to the partner device, through the management unit. The message is then compared to the expected content. A system and a graphical user interface are also included.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: April 12, 2011
    Assignee: Oracle America, Inc.
    Inventors: Ron Katz, Victor Rosenman, Yaniv Vakrat, Omer Pomerantz
  • Patent number: 7921011
    Abstract: Methods for optimizing grammar structure for a set of phrases to be used in speech recognition during a computing event are provided. One method includes receiving a set of phrases, the set of phrases being relevant for the computing event and the set of phrases having a node and link structure. Also included is identifying redundant nodes by examining the node and link structures of each of the set of phrases so as to generate a single node for the redundant nodes. The method further includes examining the node and link structures to identify nodes that are capable of being vertically grouped and grouping the identified nodes to define vertical word groups. The method continues with fusing nodes of the set of phrases that are not vertically grouped into fused word groups. Wherein the vertical word groups and the fused word groups are linked to define an optimized grammar structure.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: April 5, 2011
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Gustavo Hernandez Abrego, Ruxin Chen
  • Patent number: 7920756
    Abstract: A printer fetches a horizontal direction DCT coefficient group and a vertical direction DCT coefficient group for each block from the JPEG data. The printer selects edge patterns similar to the brightness changes expressed by these coefficient groups from a specified table, and records those pattern numbers in a RAM. The printer judges whether or not the brightness changes of the blocks with each other adjacent are continuous based on the pattern number of each block recorded in the RAM. And by connecting the edge patterns when those brightness changes are continuous, the printer accumulates the blur widths that exist extending over the blocks. Then, based on this cumulative value, the printer determines the presence or absence of image blur. It is possible thereby to detect with good precision the blur of images even for high resolution images while reducing the used memory capacity.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: April 5, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Takashige Tanaka, Ayahiro Nakajima
  • Patent number: 7921353
    Abstract: A method and system for dynamically loading content to a portion of a native global page on a client at runtime includes receiving a request at the client for the content for the portion of the native global page. The request identifies the portion of the native global page requesting the content and a type of resource required from a server. The request, identifying a server side resource to service the request, is forwarded from the client to the server. In response to the request, the client receives the identified server side resource that includes a plurality of components. The plurality of components is parsed at the client to verify the components are received in a required sequence. When it is determined that the plurality of components are received in the required sequence, a first set of components are selected from the received plurality of components and injected into a region for the portion of the native global page.
    Type: Grant
    Filed: April 9, 2007
    Date of Patent: April 5, 2011
    Assignee: Oracle America, Inc.
    Inventor: Gregory L. Murray
  • Patent number: 7916202
    Abstract: If an image reproducing apparatus has a device-dependent color space conversion function that converts the color space of processing target image data to a device-dependent color space using a particular color space, (i) reproduction image data is generated by carrying out basic color space conversion to image data for which the color space specified by color space identification information is the standard color space, and (ii) reproduction image data is generated by carrying out device-dependent color space conversion to image data for which the specified color space is the particular color space.
    Type: Grant
    Filed: February 26, 2004
    Date of Patent: March 29, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Kazunori Suenaga, Kenji Fukasawa
  • Patent number: 7913644
    Abstract: An electroless deposition system includes a deposition solution, and saturating the deposition solution with an oxygen concentration in a range from about two thousand parts per million to about twenty thousand parts per million.
    Type: Grant
    Filed: September 30, 2006
    Date of Patent: March 29, 2011
    Assignee: Lam Research Corporation
    Inventors: Ron Rulkens, Robert D. Tas, Shashank Ravindra Kulkarni, Artur Kolics, Nancy E. Gilbert
  • Patent number: 7914145
    Abstract: A progressive power lens in which distortion aberration is restricted and a manufacturing method therefore are provided. In a progressive power lens in which a progressive refracting surface provided with a first region arranged at an upper part of the lens for viewing relatively far, a second region arranged lower than the first region and having a larger refracting power than that of the first region, and a progressive zone arranged between these regions, whose refracting power is progressively changing, is formed on an inner surface of the lens, when both the far-sighted diopter and the near-sighted diopter are negative, as an upper practical region is separated from a virtual horizontal line passing through the geometric center of the lens, the curvature of the curve of the outer surface of the lens is gradually increased, while as the lower practical region is separated from the horizontal line, the curvature of the curve of the outer surface of the lens is gradually decreased.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: March 29, 2011
    Assignee: Tokai Optical Co., Ltd.
    Inventor: Hitoshi Miura
  • Patent number: 7917878
    Abstract: A number of virtual regionalization lines are laid out across a chip such that the virtual regionalization lines delineate a plurality of regions on the chip. One of the plurality of regions on the chip is designated as a master region and each of a remainder of the plurality of regions on the chip is designated as a duplicate region. A number of functional blocks are placed in the master region. Each of the functional blocks is replicated in each duplicate region by placing each functional block in each duplicate region so as to be symmetric with the corresponding functional block in the master region about the virtual regionalization lines. Wires are routed in the master region. The wires routed in the master region are replicated in each duplicate region so as to be symmetric about the virtual regionalization lines.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: March 29, 2011
    Assignee: Oracle America, Inc.
    Inventors: Dajen Huang, Yi Wu, Robert R. Brown
  • Patent number: 7913703
    Abstract: An apparatus used to supply a force onto a cleaning solution for processing a substrate for cleaning surface contaminants is disclosed. The apparatus includes a force applicator and a gate. The force applicator is configured to be adjusted to a first height off the surface of the substrate. The gate is positioned adjacent to a trailing point of the force applicator and is configured to be adjusted to a second height off of the surface of the substrate to enable planarization of the cleaning solution as the solution moves to the trailing point.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: March 29, 2011
    Assignee: Lam Research Corporation
    Inventors: Jeffrey J. Farber, Ji Zhu, Carl Woods, John M. de Larios
  • Patent number: 7917885
    Abstract: A high-level logic description is developed based on a non-primitive-based standard cell library. The logic description is synthesized into a netlist that includes references to the non-primitive-based standard cell library. A logic function for each standard cell in the netlist is determined and mapped into a set of primitive logic cells to create a primitive constructed version of each referenced standard cell. The set of primitive logic cells is defined for integration within a base array. The primitive constructed version of each referenced standard cell is included within a primitive-based cell library. The primitive-based cell library is used to place and route the netlist for the logic design for integration within the base array. The logic design is then integrated within the base array.
    Type: Grant
    Filed: January 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Tela Innovations, Inc.
    Inventor: Scott T. Becker
  • Patent number: 7913516
    Abstract: A crystalline glass with a characteristic of precipitating crystals from the surface of the crystalline glass to the interior thereof when it is being heated at a temperature higher than the softening point is used in the invention. A plurality of small crystalline glass masses 12 are accumulated and leveled in a fireproof mold coated with a mold release agent, and two crystalline glass plates 14A and 14B cut in an S shape are placed on the accumulated surface of the small crystalline glass masses 12 with the cut faces tightly bonded. A heat treatment is then performed to obtain a crystallized glass article having patterns. The crystalline glass plate can be cut into any shape to tightly bond the cut faces, and therefore the obtained crystallized glass articles have different patterns like natural-marble-like patterns, human figure patterns, animal patterns, etc. The invention also discloses a method of producing crystallized articles having patterns.
    Type: Grant
    Filed: September 21, 2009
    Date of Patent: March 29, 2011
    Assignee: Jian Quan Glass Development Company Ltd.
    Inventor: Kuo-Chuan Hsu
  • Patent number: 7909934
    Abstract: A system and method of cleaning a substrate includes a megasonic chamber that includes a transducer and a substrate. The transducer is being oriented toward the substrate. A variable distance d separates the transducer and the substrate. The system also includes a dynamically adjustable RF generator that has an output coupled to the transducer.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: March 22, 2011
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Andras Kuthi, Michael G. R. Smith, Thomas W. Anderson, William Thie
  • Patent number: 7910958
    Abstract: A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Each of the conductive features within the gate electrode level region has a width less than a wavelength of light used in a photolithography process to fabricate the conductive features. Conductive features within the gate electrode level region form respective PMOS transistor devices and respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: March 22, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 7910959
    Abstract: A cell layout of a semiconductor device includes a diffusion level layout including a plurality of diffusion region layout shapes. The cell layout also includes a gate electrode level layout defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated from each other by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The cell layout also includes a number of interconnect level layouts each defined to pattern conductive features within corresponding interconnect levels above the gate electrode level of the cell.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: March 22, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 7911213
    Abstract: A method is disclosed for calibrating a capacitance of an apparatus for measuring dielectric properties of a part. The apparatus includes an electrically grounded chamber, a lower electrode disposed within the chamber and connected to a radiofrequency (RF) transmission rod, an electrically grounded upper electrode disposed within the chamber above the lower electrode, and a variable capacitor connected to control transmission of RF power through the RF transmission rod to the lower electrode. A method is also disclosed for determining a capacitance of a part through use of the apparatus. A method is also disclosed for determining a dielectric constant of a part through use of the apparatus. A method is also disclosed for determining a loss tangent of a part through use of the apparatus.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: March 22, 2011
    Assignee: Lam Research Corporation
    Inventors: Jaehyun Kim, Arthur H. Sato, Keith Comendant, Qing Liu, Feiyang Wu
  • Patent number: 7913075
    Abstract: A method for provisioning a blade server is provided. The method includes creating a server boot image for a blade server, where the boot image includes an operating system image created from a donor server. Then, the method includes inserting the blade server into a chassis of an enclosure that is capable of receiving multiple blade servers. Then, staring the blade server from a pre-boot execution environment (PXE). The PXE loading an image that prompts a user to install a new operating system from a pre-existing target computer of the enclosure. The method then installs the new operating system. The installing includes creation of a new iSCSI target for the inserted blade server, and partitioning of the iSCSI target. The also includes restarting the inserted blade server. The restarting is configured to boot using the iSCSI target of the inserted blade server, so that the inserted blade server becomes a provisioned blade server.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: March 22, 2011
    Assignee: PMC-Sierra, Inc.
    Inventors: Dean Kalman, Jeffrey MacFarland
  • Patent number: 7908528
    Abstract: A method for aligning output from a first transmit source and a second transmit source is provided. The method includes combining complementary portions of differential signals generated from respective transmit sources to generate an output bit sequence and comparing the output bit sequence with an input bit sequence used to generate the differential signals. The method further includes adjusting one of the first or the second transmit source based on the comparison to align the output from the first and the second transmit sources. A PLD having the capability to align channels of different octets is also provided.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: March 15, 2011
    Assignee: Altera Corporation
    Inventor: Andy Turudic