Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract: An image processing method of performing a color balance correction on an image, includes: determining a first value representing color and saturation of a pixel in a skin color region of the image; generating correction amount based on the first value, a second value representing ideal color and saturation of skin, and an adjusting value for adjusting a degree of the color balance correction; performing the color balance correction on the image based on the correction amount; and outputting the corrected image. The correction amount is varied depending on an output apparatus that outputs the corrected image.

Abstract: A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes to be formed within a portion of a substrate, including a p-type diffusion region layout shape and an n-type diffusion region layout shape separated by a central inactive region. The layout of the cell also includes a gate electrode level layout defined to include a number of linear-shaped layout features placed to extend in only a first parallel direction. Each of the number of the linear-shaped layout features within the gate electrode level layout of the restricted layout region is rectangular-shaped. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The gate electrode level layout corresponds to an entire gate electrode level of the cell.

Abstract: Provided is a method, computer program and system for controlling the flow of service requests originated by a plurality of requesters. The method includes adding an additional control mechanism, which includes a serializer and a serializer queue, between the requesters and the service provider. The serializer inhibits the requesters when the serializer queue size reaches a threshold for a period proportional to the number of requesters already waiting, the queue length and the serializer service time. When the service provider queue is full or at a critical level, the serializer is inhibited for a period of time that is the approximately the difference between the service times of the serializer and the service provider. In addition, when the service provider queue is full, the service provider service time is recalculated as a function of the serializer service time and of the time required to process requests by the service provider.

Abstract: An electroplating apparatus for depositing a metallic layer on a surface of a wafer is provided. In one example, a proximity head capable of being electrically charged as an anode is placed in close proximity to the surface of the wafer. A plating fluid is provided between the wafer and the proximity head to create localized metallic plating.

Abstract: A carrier for supporting a substrate during processing by a meniscus formed by upper and lower proximity heads is described. The carrier includes a frame having an opening sized for receiving a substrate and a plurality of support pins for supporting the substrate within the opening. The opening is slightly larger than the substrate such that a gap exists between the substrate and the opening. Means for reducing a size and frequency of entrance and/or exit marks on substrates is provided, the means aiding and encouraging liquid from the meniscus to evacuate the gap. A method for reducing the size and frequency of entrance and exit marks is also provided.

Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to include rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device. Additionally, the restricted layout region corresponds to an entire gate electrode level of a cell layout.

Abstract: A technology is provided whereby correction may be carried out appropriately for both a person's face and other portions of an image, when performing color correction for image data of a photographic image in which a person appears. A process such as the following is carried out during color correction of image data of a photographic image. First, the image data of the photographic image is analyzed, and a first region which is part of the photographic image and in which a person's face is present is determined. Then, on the basis of the portion corresponding to the first region of the image data, a first parameter relating to color is calculated. On the basis of part of the image data corresponding to a second region which is part of the photographic image but different from the first region, a second parameter relating to color is calculated. The color tone of the data is then corrected on the basis of the first and second parameters.

Abstract: A restricted layout region includes a diffusion level layout including a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A total number of the PMOS transistor devices and the NMOS transistor devices in the restricted layout region of the semiconductor device is greater than or equal to eight.

Abstract: A semiconductor device includes a substrate portion having a plurality of diffusion regions defined therein. The plurality of diffusion regions are separated from each other by one or more non-active regions of the substrate portion. The plurality of diffusion regions are defined in a non-symmetrical manner relative to a virtual line defined to bisect the substrate portion. The semiconductor device includes a gate electrode level region formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the number of conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. The number of conductive features within the gate electrode level region includes conductive features defined along at least four different virtual lines of extent in the first parallel direction across the gate electrode level region.

Abstract: A wafer viewer system is provided for graphical presentation and analysis of a wafer and a wafer series. More specifically, the wafer viewer system includes a graphical user interface for displaying a wafer, graphically selecting regions of the wafer for analysis, performing analysis on the selected regions of the wafer, and displaying results of the analysis.

Abstract: A CPU divides an image into plural regions and for each of the regions, generates a histogram and calculates an average brightness Y ave. The CPU determines a focus location on the image by using focus location information, sets a region at the determined location as an emphasis region, and sets the average brightness Y ave of the emphasis region as a brightness criterion Y std. The CPU uses the brightness criterion Y std to determine non-usable regions. By using the regions not excluded as non-usable regions, the CPU calculates an image quality adjustment average brightness Y? ave, i.e. the average brightness of the entire image, with a weighting W in accordance with the locations of the regions reflected thereto, and executes a bright value correction by using the calculated image quality adjustment average brightness Y? ave.

Abstract: A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor threshold voltage of the diffusion region portion into an inoperably high transistor threshold voltage. A gate electrode is defined to extend over both the diffusion region and the implant region. A first portion of the gate electrode defined over the diffusion region forms a first transistor segment having the operable transistor threshold voltage. A second portion of the gate electrode defined over the implant region forms a second transistor segment having the inoperably high transistor threshold voltage. Therefore, a boundary of the implant region defines a boundary of the operable first transistor segment.

Abstract: A method of dynamically balancing a load on a fully connected grid (FCG) in a peer-to-peer environment includes determining if a first number of peers connected in a first FCG is greater than a preselected limit. If the first number of peers connected to the first FCG is greater than the preselected limit, then partitioning the first FCG into two or more subdivided FCGs, wherein each of the subdivided FCGs includes at least one peer connection that was previously connected in the first FCG. A subdivided location identifier can also be published for each respective resource included in each peer connection. A system for dynamically balancing a load on a fully connected grid (FCG) in a peer-to-peer environment is also described.

Abstract: Image data obtained by capturing an image including a human is received. The image data is analyzed and a part of the image including a human face is extracted. A prescribed part of the extracted human face is detected. Brightness of the image data is adjusted with reference to the prescribed part to obtain adjusted image data. An image is printed based on the adjusted image data.

Abstract: A rectangular interlevel connector array (RICA) is defined in a semiconductor chip. To define the RICA, a virtual grid for interlevel connector placement is defined to include a first set of parallel virtual lines that extend across the layout in a first direction, and a second set of parallel virtual lines that extend across the layout in a second direction perpendicular to the first direction. A first plurality of interlevel connector structures are placed at respective gridpoints in the virtual grid to form a first RICA. The first plurality of interlevel connector structures of the first RICA are placed to collaboratively connect a first conductor channel in a first chip level with a second conductor channel in a second chip level. A second RICA can be interleaved with the first RICA to collaboratively connect third and fourth conductor channels that are respectively interleaved with the first and second conductor channels.

Abstract: The embodiments provide structures and mechanisms for removal of etch byproducts, dielectric films and metal films on and near the substrate bevel edge, and chamber interior to avoid the accumulation of polymer byproduct and deposited films and to improve process yield. In an exemplary embodiment, a plasma processing chamber configured to clean a bevel edge of a substrate is provided. The plasma processing chamber includes a bottom electrode configured to receive the substrate, wherein the bottom electrode is coupled to a radio frequency (RF) power supply. The plasma processing chamber also includes a top edge electrode surrounding an insulating plate opposing the bottom electrode. The top edge electrode is electrically grounded. The plasma processing chamber further includes a bottom edge electrode surrounding the bottom electrode. The bottom edge electrode opposes the top edge electrode.

Abstract: Provided are methods for processing a substrate using a proximity system defined by one or more meniscus windows on one or more proximity heads. One method includes applying a first fluid meniscus to a surface of the substrate to apply a chemical precursor to the surface of the substrate. The first fluid meniscus is applied to first proximity meniscus window. Then, applying a second fluid meniscus to the surface of the substrate to leave an atomic layer of the chemical precursor on the surface of the substrate, through a second proximity meniscus window. A third fluid meniscus is applied to the surface of the substrate to apply a chemical reactant configured to react with the atomic layer of the chemical precursor to generate a layer of a material, through a third proximity meniscus window.

Abstract: Circuit for selectively using static or dynamic select signals inside an integrated circuit, including a first transistor connecting a static select signal to a dynamic route select output line when a dynamic select CRAM signal is at a first logical level, and a second transistor connecting a dynamic select signal to the dynamic route select output line when the dynamic select CRAM signal is at a second logical level. The circuit further comprises a dynamic select CRAM register that contains a logical value to indicate whether the dynamic select signal bypasses the static select signal. The dynamic select CRAM register is connected to the second transistor gate, and to an inverter whose output is connected to the first transistor gate.

Abstract: A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality of arcs. Each of the plurality of vectors represents possible data bits to inputs and nodes of the logic gate. The method selects a plurality of substantially distinct vectors from the plurality of vectors for each of the plurality of arcs, and performs circuit pruning for each of the plurality of substantially distinct vectors, taking each one substantially distinct vector at a time. The circuit pruning includes identifying an active circuit for each vector. The active circuit is identified by determining which circuit features are activated when applying a particular one of the substantially distinct vectors. Then, the circuit simulations limited to a plurality of transistors in the active circuit are performed.