Patents Represented by Attorney Martine, Penilla & Gencarella, LLP
  • Patent number: 7961352
    Abstract: A printing control device which performs printing control for printing by using color materials of a plurality of types, includes: acquiring unit that acquires a color material set which is a combination of the color materials used for printing; and creation unit that creates a color conversion profile which prescribes conversion rules for converting image data expressed by a first color space into image data expressed by a second color space which differs from the first color space and which is a color space expressed by a color material amount set which is a combination of usage amounts for the respective color materials constituting the color material set.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: June 14, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Nao Kaneko, Yoshifumi Arai, Takashi Ito
  • Patent number: 7961350
    Abstract: The invention provides printing method of printing on a printing medium. The method includes: generating dot data representing a status of dot formation on each of print pixels of a print image to be formed on the print medium, by performing a halftone process on image data representing, a input tone value of each of pixels constituting an original image; providing a print head having a plurality of nozzle groups that eject inks of mutually different colors; and generating the print image by mutually combining dot groups of multiple colors formed in at least one scan in a common print area, by forming each dot group with each of the plurality of nozzle groups during each scan of the print head in response to the dot data, the each of the dot groups being mutually different in color.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 14, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Toshiaki Kakutani
  • Patent number: 7961985
    Abstract: An image processing apparatus of the invention generates one still image having a high pixel density from multiple images. The image processing apparatus includes: an image extraction module that extracts the multiple images used for generation of the one still image; a deviation computation module that computes a degree of deviation between each combination of the extracted multiple images; an exclusion module that excludes any image having the computed degree of deviation out of a preset threshold range from the extracted multiple images; and an image composition module that combines remaining images other than the excluded image to generate the one still image. This arrangement of the invention ensures efficient image processing to generate one high-resolution still image from multiple images.
    Type: Grant
    Filed: May 18, 2010
    Date of Patent: June 14, 2011
    Assignee: Seiko Epson Coporation
    Inventor: Seiji Aiso
  • Patent number: 7958156
    Abstract: A method and system for mixing rich media content with textual listing on a webpage includes receiving a plurality of advertisement parameters associated with an advertisement from an advertiser. The advertisement parameters define the advertisement and are used for booking the advertisement. Additional media content associated with the advertisement is obtained from the advertiser. The additional media content includes rich media content. A dynamic content window is defined for rendering the additional media content. A graphical icon is provided for the advertisement to indicate that additional media content is available for the advertisement. The graphical icon is activated through a control or is activated by default. The graphical icon is associated with the dynamic content to provide access to the additional media content on the webpage in response to detecting a user action at the graphical icon.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: June 7, 2011
    Assignee: Yahoo!, Inc.
    Inventors: Rajendra Shriwas, Kashyap Lodhiya
  • Patent number: 7958342
    Abstract: A Nyquist sampling frequency is determined for performance counter events to be measured. Based on the Nyquist sampling frequencies, a schedule for measuring the performance counter events is determined. The performance counter event measurements are then conducted in accordance with the schedule, whereby the measurements yield a set of sample data for each performance counter event. A signal reconstruction algorithm is applied to the set of sample data for each performance counter event to reconstruct an essentially complete signal for each performance counter event. The essentially complete signal for each performance counter event is then used to improve either a design or a utilization of either a microprocessor or an application to be executed on the microprocessor.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: June 7, 2011
    Assignee: Oracle America, Inc.
    Inventors: Robert M. Lane, Kenneth Tracton, Zenon Fortuna
  • Patent number: 7958474
    Abstract: Various methods and apparatus for executing a multithreaded algorithm that performs a static timing analysis of an integrated circuit chip (chip) include logic for traversing the chip to identify a plurality of components (cells or nodes) within a chip circuit of the chip. A waveform graph is defined for the identified nodes. One or more virtual graphs are generated from the waveform graph. The plurality of nodes in the one or more virtual graphs are processed using multiple threads to obtain quadruplet of time domain dataset values representing the different modes of propagation for each node. A timing check is performed at an end node of the virtual graphs using the quadruplet of time domain dataset values to determine any timing violation within the chip design.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: June 7, 2011
    Assignee: Oracle America, Inc.
    Inventors: George J Chen, Gilda Garreton, Steven M Rubin, Robert E Mains
  • Patent number: 7956421
    Abstract: A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth gate electrodes, respectively. The fourth gate electrode is electrically connected to the third gate electrode. Each of the first P channel transistor, first N channel transistor, second P channel transistor, and second N channel transistor has a respective diffusion terminal electrically connected to a common node. Each of the first, second, third, and fourth gate electrodes is defined to extend along any of a number of parallel oriented gate electrode tracks without physically contacting a gate level feature defined within any gate level feature layout channel associated with a gate electrode track adjacent thereto.
    Type: Grant
    Filed: March 11, 2009
    Date of Patent: June 7, 2011
    Assignee: Tela Innovations, Inc.
    Inventor: Scott T. Becker
  • Patent number: 7958468
    Abstract: A method for indentifying instances of a smaller circuit in a larger circuit is disclosed. Both the smaller circuit and the larger circuit have a plurality of vertices. A vertex is one of a device or a net. The device, such a transistor, includes a Gate, a Drain, and a Source. The net is a wired connection between devices. In this method, one initial unique label is assigned to each of the plurality of vertices, each of a plurality of connection-types, power connection, and ground connection. A zero label is assigned to each of an input/output ports and a same initial unique label is assigned to same types of circuit components. Then each net is relabeled using labels of neighboring vertices. The neighboring vertices of a vertex are vertices that are directly connected to the vertex. Then, each device in the plurality of vertices is relabeled using labels of neighboring vertices excluding a label of a vertex that is connected to the Gate of the each device.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Oracle America, Inc.
    Inventor: Douglas C. Meserve
  • Patent number: 7957031
    Abstract: An image processing method involves processing image data indicative of an image represented with a prescribed number of input tones by each of pixel groups composed of a plurality of print pixels, and generating dot data representing a status of dot formation on each of the print pixels to be formed on a print medium. The method includes preparing a first conversion table and a second conversion table, determining the pixel group tone value in response to the input tone value corresponding to the pixel group, converting the determined pixel group tone value into the code values for each of the pixel groups, by referring to the first conversion table, decoding the acquired code value into the output dot arrangement for each of the pixel groups, by referring to the second conversion table, and outputting the dot data in response to the output dot arrangement.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: June 7, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Toshiaki Kakutani
  • Patent number: 7957142
    Abstract: Apparatuses, methods, and systems directed to efficient cooling of data centers. Some embodiments of the invention allow encapsulation of cold rows through an enclosure and allow server fans to draw cold air from the cold row encapsulation structure to cool servers installed on the server racks. In other particular embodiments, the systems disclosed can be used to mix outside cool air into the cold row encapsulation structure to cool the servers. In some embodiments, the present invention involves using multiple cold row encapsulation structures to cool the servers installed on the racks.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: June 7, 2011
    Assignee: Yahoo! Inc.
    Inventors: Scott Noteboom, Albert Dell Robison, Jesus Suarez, Norman Holt
  • Patent number: 7958285
    Abstract: A system and method of deterministically transferring data from a first clock domain to a second clock domain includes writing data to a buffer, communicating a read status from the first clock domain to the second clock domain and reading data from the buffer into the second clock domain at a clock rate of the second domain. The buffer is accessible by both one or more devices in each of the first clock domain and the second clock domain and the read status is communicated from the first clock domain to the second clock domain when the second clock domain enables the read status to be communicated from the first clock domain to the second clock domain.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: June 7, 2011
    Assignee: Oracle America, Inc.
    Inventors: Frank C. Chiu, Ian Jones, Anup Pradhan
  • Patent number: 7955083
    Abstract: A system and method of an atomic tile including an elemental symbol for a corresponding element and a dot representation of at least one valance electron of the corresponding element. The dot representation are proximate to corresponding edges of the octagonal shape.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: June 7, 2011
    Assignee: California Polytechnic Corporation
    Inventor: Seth D. Bush
  • Patent number: 7953581
    Abstract: A system and method of analyzing a power grid in an integrated circuit includes inputting a circuit design to a test bench, inputting a plurality of initial values for the circuit design in to the test bench, setting a current time t to 0 value for an initial time (t0) of the operation of the circuit design, representing each capacitor in an RC circuit corresponding to the power grid circuit design by the each capacitor's respective time variant equivalent companion model, describing each one of the plurality of RC equivalent circuits mathematically as one of a corresponding plurality of linear equations, storing the plurality of linear equations in a matrix Y0 for time t0, resolving the matrix Y0 to determine a DC operating point, updating the RC equivalent circuits and the corresponding plurality of linear equations at a second time step t1=t+h where h is a time step value equal to the current time t and a next simulated operation time, storing the updated plurality of linear equations in a matrix Y1 for ti
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: May 31, 2011
    Assignee: Oracle America, Inc.
    Inventors: Michael Yu, Alexander I. Korobkov
  • Patent number: 7952757
    Abstract: A system is configured to calculate an evaluation index of sample ink amount data from a color difference evaluation index and an image quality evaluation index and create a profile on the basis of a sample with a high rating value. When the image quality evaluation index is predicted, the image quality evaluation index corresponding to any sample ink amount data is estimated based on a profile produced on the basis on actual evaluation. A printer driver is configured to create a plurality of profiles by using different indices in this system and to perform color conversion by using the plurality of profiles. The plurality of profiles are appropriately selected according to the user's needs, printing conditions, and type of printing object image.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: May 31, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Nao Kaneko, Yoshifumi Arai
  • Patent number: 7952387
    Abstract: A memory initialization file and one or more design files associated with configuring an IC are identified. The memory initialization file is encrypted using one or more encryption algorithms. A configuration bit stream is generated by compiling and assembling the encrypted memory initialization file and the one or more design files. During the programming phase, the configuration bit stream is received at the IC, decoded and logic design and content of encrypted memory initialization file are loaded into the respective logic elements and memory arrays of the IC. The IC then transitions into a user phase where the contents of the encrypted memory initialization file in the memory arrays are decrypted and validated at the on-chip memory within the IC to ensure that the integrity of the content is maintained. Upon successful verification of the integrity of the content, the content within the on-chip memory is available for processing.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: May 31, 2011
    Assignee: Altera Corporation
    Inventor: Rodney Frazer
  • Patent number: 7952617
    Abstract: The image processing device performs image processing using image data generated by an image generating device, and image generation record information associated with the image data where the image generation record information includes at least operating information about the image generating device at the time of generation of the image data. A picture quality adjuster is able, when the image generation record information includes subject brightness information relating to the brightness of a subject at the time of generation of the image data, to adjust the picture quality of the image data using the subject brightness level derived from the subject brightness information.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: May 31, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Makoto Fujino
  • Patent number: 7954006
    Abstract: A method and system for preventing loss of data in a computer interface board during power failure includes providing a secondary data path to a non-volatile storage element from a cache memory of the computer interface board. Components in the secondary data path, such as the cache memory and non-volatile storage element, are powered by a secondary power supply. The cache memory of the computer interface board is a volatile memory. The secondary data path with the non-volatile storage element enables reliable memory operation during both normal and power fail modes. A power failure at the computer interface board is detected. The power failure may result in incomplete transactional data within the cache memory. Upon detection of power failure, the incomplete transactional data at the cache memory is transmitted to the non-volatile storage element through the secondary data path using the power from the secondary power supply.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 31, 2011
    Assignee: PMC-Sierra, Inc.
    Inventor: Prasad Mangipudi
  • Patent number: 7952119
    Abstract: A restricted layout region includes a diffusion level layout that includes a number of diffusion region layout shapes to be formed within a portion of a substrate of a semiconductor device. The diffusion region layout shapes define at least one p-type diffusion region and at least one n-type diffusion region. The restricted layout region includes a gate electrode level layout defined to pattern conductive features within a gate electrode level above the portion of the substrate. The gate electrode level layout includes rectangular-shaped layout features placed to extend in only a first parallel direction. Some of the rectangular-shaped layout features form gate electrodes of respective PMOS transistor devices, and some of the rectangular-shaped layout features form gate electrodes of respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the restricted layout region of the semiconductor device.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: May 31, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Michael C. Smayling
  • Patent number: 7952359
    Abstract: First and second resistors are provided between a first input/output terminal and a power supply terminal, and between a second input/output terminal and the power supply terminal, respectively. Third and fourth resistors are connected to the second and first input/output terminals, respectively. First and second current-switching switches couple either the first input/output terminal side or the second input/output terminal side with a first current source and a second current source, respectively, according to the value of pattern data. A level shift circuit shifts the electric potentials at the second terminals of the third and forth resistors by a predetermined level. A comparator circuit compares the electric potentials at the second terminals of the third and fourth resistors level-shifted by the level shift circuit with those at the second terminals of the fourth and third resistors, respectively, and generates first and second comparison signals according to the comparison results.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: May 31, 2011
    Assignee: Advantest Corporation
    Inventor: Shoji Kojima
  • Patent number: 7953297
    Abstract: The procedure of the present invention estimates a correction rate for elimination of a positional shift between the multiple first images, executes correction with the estimated correction rate to eliminate the positional shift between the multiple first images, and combines the multiple corrected first images to generate the second image. The procedure selects a target pixel among pixels included in the second image, and detects multiple adjacent pixels respectively in the multiple first images, which adjoin to the selected target pixel. The procedure then selects an image as a composition object or a composition object image with regard to the target pixel among the multiple first images according to the multiple adjacent pixels, and calculates a pixel value of the target pixel based on the composition object image.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: May 31, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Seiji Aiso