Abstract: A pressure booster and method for amplifying a water pressure that is supplied by a water facility is provided. The pressure booster is configured to be connected between the water facility and one or more semiconductor substrate cleaning systems. The pressure booster includes a pump having a pump input that connects to the water facility and a pump output that is configured to produce a fluctuating amplified water pressure that is greater than the water pressure that is supplied by the water facility. Further included is a pressure dampener having a dampener input for accepting the fluctuating amplified water pressure from the pump output. The pressure dampener is configured to partially reduce pressure fluctuations in the fluctuating amplified water pressure. The pressure dampener also has a dampener output. A pressure regulator having a regulator input for receiving the dampener output is also included as part of the pressure booster.

Abstract: A system and associated method for authorizing, or withholding authorization of, user access to a selected computer application or other resource, based on the user's response to one or more user authentication tests. If the user is presented with two or more authentication tests, each with an associated test weight, the system optionally sums the weights of the tests satisfied by the user; and if this sum is greater than a selected test score threshold, the user is granted access to the resource. Alternatively, the user is granted access to selected subsets of the application, including an empty or non-empty default subset, depending upon the sum of the weights of the tests satisfied by the user. An authentication test or its associated weight may change at a selected time, and the selected time may be determined with reference to a time at which the resource changes. A smartcard may be used to respond to one or more authentication tests.

Abstract: The present invention provides a dual mode clock alignment device including a clock buffer cell, a PLL, and a first set and second set of buffers. The clock buffer cell is arranged to receive a first clock and delays the first clock. The PLL is arranged to receive the delayed first clock from the clock buffer and outputs a second clock. The first and second sets of buffers are arranged to receive the delayed first clock from the clock buffer cell for operating in a first clock mode. The first and second sets of buffers are further arranged to receive the second clock from the PLL for operating in a second clock mode. In this arrangement, the first set of buffers delays the received clock by a first delay to output a third clock and the second set of buffers delays the delayed clock by a second delay to output a fourth clock. When operating in the second clock mode, the first, third, and fourth clocks are all aligned.

Abstract: Methods for maintaining consistent data and attributes for files sharable by two or more consumers are provided. One exemplary method includes initially defining a set of consistency bits that are implemented by a file consistency protocol. Once the consistency bits are defined and implemented by a file system managing the shared files, the method receives indication that a change was made to a file associated with the file system. The method then sets a bit of the set of consistency bits on each instance file to reflect the change performed to the file. An update is then messaged to each instance file such that the instance files contain the change made to the file. The messaging can be performed by way of a pulling protocol or a push protocol, which transfers the updates to the instances to maintain the consistency.

Abstract: A method for generating a database of data resident on a primary storage device of a computer system for use in a backup system associated with the computer system includes generating a database having information associated with data resident on the primary storage device of the computer system. A graphical user interface is then generated to display the information in the database. The displayed information is preferably configured to be selected by a user to define a backup set of data that is available to be copied from the primary storage device of the computer system to a secondary storage device connected to the computer system. The method may further include the operations of setting a flag to designate selected portions of the database, and writing the selected portions of the database to the primary storage device of the computer system.

Abstract: A package for holding a compact disc (CD). The package is defined by a unitary package piece that is divided into a set of sections, and each of the set of sections is capable of having printed data thereon. The unitary package piece includes a CD holding section defined by a section of the unitary package piece. The CD holding section having a pair of CD support flaps and a CD access cut-out. A set of four sections are part of the unitary package piece, and the set of four sections are defined by a first fold line and a second fold line. The CD holding section is configured to fold and adhere to one of the set of four sections, and the set of four sections are configured to define the package when folded along the first fold line and the second fold line. A locking flap is integral with one of the four sections of the unitary package piece, and the locking flap is configured to hold the package together when folded along the first fold line and the second fold line.

Abstract: A TFT LCD and the method of making the same are provided to prevent short circuits occurred between metal lines and transparent pixel electrodes. An insulating layer is provided to overlay the entire metal layer except the intersection areas for forming contact windows. Then, the transparent conductive layer is provided to form pixel electrodes and interconnection lines. Thus, even transparent conductive layer is not etched clearly and forming residuals, the residuals will not cause short circuits between the metal lines and transparent pixel electrodes. Eventually, the production yield rate can be increased. Moreover, a second metal layer is deposed under the transparent conductive layer to reduce the resistance of the interconnection lines.

Abstract: A system, method and apparatus for comparing two floating point numbers is includes choosing a first floating point number and a second floating point number to be compared. The first number is sign extended one bit to create a first sign extended number. The second number is sign extended one bit to create a second sign extended number. The second sign extended number is subtracted from the first sign extended number to determine a subtraction result. The sign bits for said first number and said second number are examined to determine if they are both ones. If the sign bits for the first number and the second number are both ones, the sign bit of the subtraction result is inverted to create a final result. If the sign bit of the final result is a zero, asserting that the first number is greater than or equal to the second number. Alternatively, if the sign bit of the final result is a one, asserting that the first number is less than the second number.

Abstract: The present invention provides a system and method for reading a SRAM unit having a first SRAM way and a second SRAM way with a read control system, a way select macro and a word select macro. The word select control macro is configured to select one of the plurality of words. The way select control macro is configured to select either the first SRAM way or the second SRAM way. The system and method employ a read logic controller having a word select function and a way select function. The read logic controller is operatively coupled to a read counter, a word counter, and an address counter.

Abstract: Methods for maximizing recording efficiency when recording data from a source to an optical media are provided. In one example, a method includes identifying a list of files to be recorded, and then generating a plurality of recording orders for the list of files. A plurality of writing speeds supported by a target optical media recording device are determined, and then each of the plurality of recording orders for the list of files at each of the plurality of writing speeds are evaluated to determine the amount of system cache required and the projected recording time for recording the data. The method selects a single recording order and a single writing speed that minimizes system cache utilization and minimizes actual recording time to record the data from the source to the optical media.

Abstract: A wafer processing module is provided. In one example, the wafer processing module includes a sub-aperture CMP processing system and a pad exchange system including a pad magazine for storing CMP processing pads and a pad exchange robot for transferring CMP processing pads between the sub-aperture CMP processing system and the pad magazine. The wafer processing module includes a module frame that integrates the sub-aperture CMP processing system including the pad exchange system, with a wafer scrubber unit and a wafer SRD unit.

Abstract: One or more embodiments provide the ability to use multiple path formats in an object oriented system. A path maintains the ability to translate itself into a recognizable format for use by applications. The recognizable format may be a standard Bezier Path format or an iterator that provides the ability to iterate along the path, one curve segment at a time. Multiple applications may use the self-translation ability. In one embodiment, when an application desires to perform a transform, it determines if the transform may be performed on the path (i.e., whether the path is recognizable). If the path is recognizable, the transform is performed directly on the path. If the path is not recognizable, the path translates itself into a recognizable format and the transform performs the action on the recognizable path (the transform must maintain the ability to perform the transform on the standard format). Determining whether the path is recognizable may consist of a two stage negotiation process.

Abstract: A peripheral device having a protocol communication chip is provided. The protocol communication chip is configured to manage communication between the peripheral device and a host computer over a serial bus. The protocol communication chip includes a bus interface and a link control and status register. The link control status register is provided for setting link parameters, and is configured to be either read or written by the host computer by the transmission of a 16 byte packet having a DataType 0. The 16 byte packet is an OUTDATA packet for control and an INSTART packet for status. The peripheral device is configured to receive device command information from the host computer using a DataType 1 packet, and host computer being configured to access data resident on the peripheral devices using a DataType 2 packet.

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed by the CPU with modified op codes. As a result, it is unnecessary to decrypt the program into standard op codes prior to execution. The modified op codes are provided with surplus bits, causing an increase in op code length, and the output of data results is provided in blocks of several words. The internal allocations of signals and logic gates is made key dependent to further foil the efforts of adversaries who may attempt to understand the program instructions.

Abstract: A speed variation mechanism includes a base, a first sliding member, a second sliding member and a fixing device. The base has a first surface. The first sliding member is able to slide on the first surface and has a second surface. The second sliding member is able to slide on the second surface and has a third surface. The third surface is in contact with a driven member to drive an optical device. The fixing device can selectively fix the first sliding member to the base or the second sliding member. When the second sliding member is pushed, the speed variation mechanism of the invention can provide different moving speeds for the driven member to drive the optical device by fixing the first sliding member to the base or the second sliding member.

Abstract: A metal programmable ROM includes a memory cell array having a depth defined by a plurality of wordlines and a width defined by a plurality of bitlines. In addition, a group of memory cells are coupled between a bitline and a ground conection, with each memory cell in the memory cell group coupled to at least one other memory cell in the memory cell group. Finally, a programmed memory cell is defined by a memory cell transistor having its terminals shorted together.

Abstract: A partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip. Therefore, the partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer.

Abstract: An optical switch includes two optical input terminals, two optical output terminals, two reflecting devices and a movable device. The optical input terminals are used to receive light rays. The two reflecting devices are positioned at fixed positions, and the movable device reflects light rays. When the position of the movable device moves, the light rays are reflected by one of the reflecting devices and are selectively output from the optical output terminals.

Abstract: An invention is provided for removing a top wafer layer during a CMP process. Time series data is collected based on a reflected wavelength from a top layer of a wafer. A Fourier Transform is applied to the time series data, and a frequency of peak intensities in the Fourier Transform of the time series data is analyzed to determine a peak magnitude in the frequency. A first removal rate of the top layer is determined based on the peak magnitude in the frequency, and a current thickness of top layer is calculated based on the first removal rate. The CMP process is discontinued when the current thickness of the top layer is equal to or less than a target thickness, and a separate polishing process is performed to remove an additional portion of the top layer. In one aspect, the separate polishing process can be based on a soft endpoint detection process having second removal rate that is lower than the first removal rate.

Abstract: A single-ended high-voltage level shifter for a TFT-LCD gate driver comprises a high-voltage power supply and a low-voltage power supply, a low-voltage NMOS transistor, a high-voltage NMOS transistor, and a high-voltage PMOS transistor. An input signal is applied at the gate of the low-voltage NMOS transistor. The source of the low-voltage NMOS transistor is connected to the low-voltage power supply. The source of the high-voltage NMOS transistor is connected to the drain of the low-voltage NMOS transistor. The high-voltage NMOS transistor has a first reference voltage applied at its gate. The level of the first reference voltage is between the input-signal level and the high-voltage power supply. The drain of the high-voltage PMOS transistor is connected to the drain of the high-voltage NMOS transistor. The source of the high-voltage PMOS transistor is connected to the high-voltage power supply. The high-voltage PMOS transistor has a second reference voltage applied at its gate.