Abstract: Methods for rinsing and drying a substrate are provided. In one example, a method for rinsing and drying a substrate includes providing a substrate for processing and securing the substrate in a hollow spin chuck. The hollow spin chuck with the substrate positioned therein is rotated at a first rate of rotation while a rinsing agent and a surface tension modifying agent are dispensed at a position that is an approximate center of the spinning substrate on both an active surface and a backside surface of the substrate. The dispensing is moved from the approximate center of the spinning substrate radially outward towards a periphery of the substrate. The dispensing is then discontinued, and the hollow spin chuck with the substrate positioned therein is rotated at a second rate of rotation.

Abstract: An invention is provided for a chemical mechanical planarization apparatus. The apparatus includes a cylindrical frame, a polishing membrane attached to an end of the cylindrical frame, and a pad support disposed within the cylindrical frame and below the polishing membrane that is capable of differentially flexing the polishing membrane. The pad support can be air bearing that provides air pressure to the polishing membrane to differentially flex the polishing membrane during a CMP process. In a further aspect, the pad support can be in contact with the polishing membrane, and include mechanical elements that are capable of differentially flexing the polishing membrane during a CMP process. In addition, the apparatus can include a conditioner element disposed above the polishing membrane, and a conditioner pad support disposed below the polishing membrane and the conditioner element, wherein the conditioner element is capable of eroding the polishing membrane.

Abstract: A method for partitioning end nodes on a fabric is provided. The method includes configuring a storageless host on the fabric. The storageless host is configured by loading a programming media which has host programming code onto the host. The host programming code is configured to provide the storageless host access to the fabric. The method also includes searching for available end nodes that are connected to the same fabric as the host. After available end nodes are discovered on the fabric, the user selects a desired available end node which is connected to a storage device. The desired available end node is associated with the host on the fabric after the user selects the desired available end node. A management function then installs a partitioning key at the desired available end node and a matching partitioning key at the host. The matching partitioning key installed at the host matches the partitioning key installed at the desired available end node.

Abstract: A invention is disclosed that provides intelligent failover in a multi-path computer system. Initially, a plurality of data paths to a computer input/output (I/O) device is provided, wherein the plurality of data paths to the computer I/O device are represented as a single logical computer I/O device. Then, during operation, an I/O request to access the computer I/O device is intercepted. A data path from the plurality of data paths to the computer I/O device is then selected, and the computer I/O device is accessed using the selected data path.

Abstract: An invention is provided for spindle downforce calibration. The system includes a calibration wafer carrier having a calibration load cell recess, and a calibration load cell disposed within the calibration load cell recess. The system further includes a meter in communication with the calibration load cell. In operation, the calibration load cell measures a downward force applied to the to the calibration wafer carrier. The measurement can be taken when the calibration wafer carrier is positioned substantially at a polishing height, which is substantially equivalent to a height of a normal wafer carrier during a chemical mechanical polishing (CMP) operation. In one aspect, the measured downward force is compared to a tool downward force measurement that is measured using a tool load cell, which is generally utilized to measure tool downward force during a normal CMP process.

Abstract: The invention provides a memory device including a memory substrate, an insulating layer, a shielding metal layer, a second dielectric layer and a second metal layer. The memory substrate includes a substrate, a memory cell area, a peripheral circuit area, a first dielectric layer and a first metal layer. The first dielectric layer is formed on the memory area and the peripheral circuit area, which are formed on the substrate. The first metal layer is formed on the first dielectric layer while the insulating layer is formed on the first dielectric layer not covered with the first metal layer. The shielding metal layer is formed on the insulating layer over the memory cell area. The second dielectric layer is formed on the shielding metal layer, the insulating layer not covered with the shielding metal layer and the first metal layer not covered with both the shielding layer and the insulating layer. The second metal layer is formed on the second dielectric layer.

Abstract: A method for image processing in a computerized system reduces the amount of memory required for image processing and produces a layered effect which permits complex manipulation such as scaling and rotation without long delay, while allowing earlier versions of the visual image to be recalled. The method involves pre-processing, image editing and raster image processing.

Abstract: Methods and apparatus for facilitating the sharing of graphics rendering operation implementations between different pixel formats. A lookup table is generated that stores the descriptions of the various rendering operation implementations. A plurality of chains of inherited object descriptors allows traversal from specific to more general descriptions of pixel formats and composition operations. Using these chains, the lookup table can be searched for a rendering operation implementation that best matches the specified criteria.

Abstract: A semiconductor process recording apparatus comprises a buffer circuit and a endpoint recording device. The input terminal of the buffer circuit is connected to an external endpoint apparatus for receiving a first signal output from the endpoint apparatus. The output terminal of the buffer circuit is connected to the endpoint recording device for outputting a second signal representative of the first signal in response to the first signal. When receiving the second signal, the endpoint recording device outputs a feedback signal to the buffer circuit on the basis of the second signal. Because the feedback signal is blocked by the buffer circuit, the external endpoint apparatus is protected from the damage caused by the feedback signal, thereby greatly reducing the production cost and rate of semiconductor manufacturing.

Abstract: A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Register Domains may have different types of execution units within them. Individual Register Domains will be visible to a user.

Abstract: A transmission mechanism for an optical device is provided to change an angle of an optical element. The transmission mechanism includes a first member and a second member. The first member has a slanted surface and is capable of sliding back and forth along a first direction. The second member has a first part and a second part. The first part is contacted with the slanted surface of the first member. The second part has one end connected with the first part and the other end connected to the optical element. When the first member moves, the first part contacting the slant surface moves relative to the slanted surface, thereby causing the second part to rotate so as to change the angle of the optical element.

Abstract: A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the CPU with its operation modified. In order to execute program instructions, the buffer interdependencies must match that expected by the compiler. This makes analysis of the program operation extremely difficult. The instruction buffer on a keyed microprocessor contains logic which is able to route a subset of the instruction bits on the microprocessor. This selects destination logic gates in the microprocessor which eventually reach a programmable instruction decoder and an instruction buffer interdependency checking logic block.

Abstract: Scheduling is performed for a switch fabric (e.g., an input-buffered switch fabric). A first input port from a set of input ports is selected, for a first output port, based on a weight value uniquely associated with each link from a first set of links. Each link from the first set of links are between the first output port and a unique input port from the set of input ports. A second output port from a set of output ports is selected for a second input port.

Abstract: CMP systems and methods provide necessary vacuum and pressure to be applied from a vacuum chuck through a carrier film to a wafer without interfering with desired wafer planarization during CMP operations. Prior low polish rate-areas on the wafer may be eliminated from an exposed surface of the wafer by structure to uniformly compress the carrier film in response to a force from the wafer on the carrier film during the CMP operations. A distance between, and diameters of, adjacent holes of the carrier film are reduced, and the locations of the holes are in an array to coordinate with passageways through the vacuum chuck. The structure significantly reduces a maximum value of compression of the carrier film during CMP operations. As a result, during the CMP operations the wafer does not deform in a manner that exactly matches the compression of the carrier film, but remains essentially flat.

Abstract: One polishing media for chemical mechanical planarization includes an underlayer and a plurality of pressure sensors provided on the underlayer. At least some of the pressure sensors have a pad asperity provided thereon. The pressure sensors may be micro electromechanical systems (MEMS) pressure transducers or MEMS thermal actuators that monitor at least one of localized strain and temperature variation. Another polishing media includes a plurality of chemical sensors. Yet another polishing media includes pressure sensors, chemical sensors, and piezoelectric elements. Based upon the sensory outputs received from adjacent sensors, the piezoelectric elements provide active control to the process input by, for example, inducing localized vibration to modify the spatial removal behavior, inducing localized electric fields, or inducing localized heating/cooling elements.

Abstract: An invention is provided for a CMP apparatus that enhances removal rate uniformity. The CMP apparatus includes a polishing belt disposed below a carrier head that is capable of applying a wafer to the polishing belt. Also included is a platen disposed below the polishing belt. The platen includes a circular shim section disposed on the top surface of the platen. The circular shim section is higher than the top surface of the platen. When using this configuration, increasing pressure to the backside of the polishing belt decreases the edge removal rate of the wafer. Conversely, decreasing pressure to the backside of the polishing belt increases the edge removal rate of the wafer.

Abstract: An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.

Abstract: An edge roller assembly includes first and second grip rings. The grip rings are held together in an opposing relationship such that outer surfaces thereof define a groove for receiving an edge of a substrate. The grip rings may be O-rings formed of a rubber material. In one embodiment, the grip rings are held together by lower and upper clamp plates that are adjustably fastened together so that the clamping forces exerted on the substrate can be controlled. The upper clamp plate may have a height adjustment knob for adjusting the height of the edge roller assembly mounted thereon. A method for contacting an edge of a substrate and a transport system for transporting semiconductor wafers to a wafer processing station also are described.

Abstract: The present invention provides methods for automatically assigning addresses to expanders in a computer I/O subsystem that is coupled to one or more host computers. The computer I/O subsystem includes one or more peripheral buses, a set of peripheral devices, and a set of expanders with each expander being arranged to couple a pair of peripheral buses. The peripheral devices are coupled to the peripheral buses. In this configuration, a host computer selects a peripheral device as a target device and writes an address data pattern to the selected target device. The host computer then selects the target device and reads the address data pattern from the target device. Unique addresses are then assigned to one or more expanders coupling the host computer and the target device starting from the address data pattern, preferably by incrementing the address data pattern.

Abstract: A method and system for operating a photo kiosk having a scanner therein, including positioning a user-provided picture on a scanner bed of the kiosk scanner in an arbitrary orientation, and automatically determining an orientation of the picture by pre-scanning, using the kiosk scanner, at least an area of the kiosk scanner bed having the picture positioned therein at a low resolution, to produce a pre-scanned image containing pixels therein, and scanning, using the kiosk scanner, an area of the scanner bed at a high resolution to provide a photo product having the picture in a desired orientation therein irrespective of the arbitrary orientation.