Abstract: A structure and method for forming a semiconductor structure includes forming a plurality of device layers on a substrate (the device layers including a blocking layer having a thickness correlating to a magnitude of implant attenuation), removing the blocking layer from selected devices of the semiconductor, and implanting an impurity into the substrate, the device layers and partially through the blocking layer.

Abstract: A semiconductor memory device includes a floating gate, a control gate, source and drain regions, a lightly doped region of the second conductivity type, and a silicide layer. The floating gate is formed on a semiconductor substrate of the first conductivity type via a gate insulating film. The control gate is formed on the floating gate via an insulating film. The source and drain regions are formed by diffusing an impurity of the second conductivity type in the surface of the semiconductor substrate on the two sides of the floating gate. The lightly doped region is formed with a surface exposed at a position distant from the floating gate in at least the source region. The lightly doped region has an impurity dose lower than that of the source region. The silicide layer is formed on the exposed surface of the lightly doped region.

Abstract: In a multiple determination apparatus for determining whether or not a dividend is a multiple of a divisor which is represented by D=.alpha..multidot.2.sup.r where .alpha. is an odd number and r is 0, 1, 2, . . . , a non-zero determination circuit determines whether or not a remainder of a division of the dividend by 2.sup.r is zero. A selector circuit replaces a first number with a quotient of the division. An operational circuit determines whether or not a greatest common measure between .alpha. and the first number coincides with .alpha., when the remainder is zero. Thus, it is determined that the dividend is a multiple of the divisor when the greatest common measure coincides with .alpha..

Abstract: A multiphase clock generating circuit having: a clock generating section for generating N-phase clock signals of number N which have a frequency nearly equal to that of input clock signal and whose phases are sequentially shifted by 360 degrees/N; an input side M-division circuit that divides the frequency of the input clock signal by M, outputting a reset signal to the clock generating section; an output side M-division circuit that is fed with a delayed reset signal that the reset signal output from the clock generating section is accompanied with a predetermined delay, and, synchronized with the delayed reset signal, divides the frequency of output clock signal output from the clock generating section by M; and a controller for comparing the input side M-division clock and the output side M-division clock, and controlling a delay amount of the clock generating section based on the comparison result.

Abstract: A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a transistor-level net list for the circuit to be verified, information concerning partial circuit networks that form part of a circuit to be verified, a maximum resistance calculating part for calculating, based on the information concerning the partial circuit network, the maximum resistance that occurs while the channel connected component is operating, a gate capacitance calculating part for calculating, based on the information concerning the partial circuit network, the total gate capacitance for the portions but the inverter of a driven circuit, and an error judging part for calculating the value of evaluation function, based on the value of maximum resistance and the total gate capacitance, and judging whether or not the calculated value is in violation

Abstract: A semiconductor device having two or more types of separation oxide film are formed on the substrate of the semiconductor device by different methods so as to correspond with element types formed on the same semiconductor substrate. The method for producing the semiconductor device comprises a first separation oxide film formation process, and a second separation oxide film formation process. In the first separation oxide film formation process, a first mask layer is formed on the semiconductor substrate, the first mask layer of the element separation region of the logic element is selectively removed and the semiconductor substrate in the region area selectively oxidized. In second separation oxide film formation process, the remaining first mask layer is removed, a second mask layer is formed, the second mask layer of the element separation region of DRAM elements is then selectively removed, and the semiconductor substrate of the region is selectively oxidized.

Abstract: A phase locked loop circuit comprises a voltage controlled oscillator generating an output signal having the frequency controlled by an applied control voltage, a comparing circuit for comparing an input signal with the output signal of the voltage controlled oscillator in phase or in frequency, and a charge pump and loop filter receiving an output signal of the comparing circuit for generating the control voltage applied to the voltage controlled oscillator. A control circuit is additionally provided which receives the output signal of the comparing circuit for controlling, on the basis of a pulse width of the output signal of the comparing circuit, a center frequency of a phase locked loop formed of the voltage controlled oscillator, the comparing circuit and the control voltage outputting circuit. Thus, the PLL circuit constructed of only a simple digital circuit and having an enlarged capture range and a high stability, can be realized.

Abstract: A method of mounting a semiconductor element on a substrate and a semiconductor device formed therewith, includes forming mounting pads on the substrate, roughening a surface of at least one of the pads, positioning a resin between a semiconductor element having electrodes formed thereon and the substrate, and connecting roughened surfaces of the pads to the electrodes, respectively.

Abstract: An output buffer control circuit in which an amplitude of a gate input of a MOS transistor for the output's sake is variable by virtue of a program or a mask option, thus there is no electromagnetic interference caused by excessive output current and unnecessary current consumption, is suitable in use for universal integrated circuit. A gate voltage selector circuit selects one out of three voltages (V.sub.DD +.alpha.), V.sub.DD, and (V.sub.DD -.beta.) in accordance with the combination of selection signals S.sub.1, S.sub.2, and S.sub.3. A level conversion circuit performs ON-OFF of a voltage V.sub.1 selected by the gate voltage selector circuit in accordance with a source output signal to be outputted to an outer section with the same cycle as the source output signal, thus communicating it as a gate input to an n-MOS transistor of an output buffer. It is equivalent to that it causes amplitude V.sub.DD of the source output signal to be performed level conversion toward the voltage V.sub.

Abstract: In a semiconductor device which includes at least an interlayer insulating film containing a plurality of Si--H bonds, a Si--OH bond portion is removed from a surface of the interlayer insulating film.

Abstract: An optical coupling module includes first, second, and third substrates, first and second optical fibers, and first and second lenses. The first substrate has a surface formed with a first V-groove. The second substrate has a surface formed with a second V-groove. The third substrate is arranged between the first and second substrates and has a surface formed with first and second recess. The first to third substrates have the surfaces flush with each other. The first and second optical fibers are fixed in the first and second grooves, respectively, and are arranged such that their end faces oppose each other. The first and second lenses are fixed in the first and second recesses, respectively, and are arranged on one optical axis of the first and second optical fibers to be spaced apart from each other by a predetermined distance.

Abstract: This invention discloses a way to map IP or similar routing information onto a technology that uses label switching and swapping, such as ATM, without the need to change the network paradigm. This allows a network to continue to function and appear as a standard IP network, but with much higher performance. One of the requirements of IP networks is to decrement the IP packet Time-To-Live (TTL) field on each hop it traverses. Currently, switched packets within an ATM like network cannot decrement the TTL. This invention can decrement packet TTLs appropriately by maintaining a hop-count per each switched path. This hop-count maintains the total number of hops a packets would have traversed, had it been forwarded in the IP hop-by-hop model, rather than through the ATM like switched path. Before forwarding a packet on a switched path, an ingress ISR decrements the TTL by the hop-count. In this way, at the switched path exit point, the TTL is the same as if it had been forwarded by IP.

Abstract: An over-sampling type clock recovery circuit includes a phase difference detecting section, a phase adjusting section and a signal selecting section. The phase difference detecting section detects a phase difference between a data signal and each of a plurality of active sets of clock signals, and generates a phase adjustment signal from a plurality of phase difference data corresponding to the detected phase differences using a majority determination. The phase adjusting section generates N (N is an integer equal to or larger than 2) sets of clock signals and adjusts phases of clock signals of the N sets based on the phase adjustment signal. The signal selecting section selects a part or all of the N sets of clock signals based on the detected phase differences from the phase difference detecting section. The selected sets of clock signals are supplied to the phase difference detecting section as the plurality of active sets of clock signals.

Abstract: A magnetic switching device, includes a first electrode, a second electrode, and a nanoparticle having a magnetic moment and being disposed between the first and second electrodes. At least one of the first electrode and the second electrode includes a magnetic material which has a net spin polarization in its conduction band for injecting, into the nanoparticle, an electrical current including a net spin polarization for overcoming the magnetic moment of the nanoparticle upon selection of a predetermined magnitude for the electrical current.

Abstract: Measurement of pulse CV characteristics and an SIMS measurement of a semiconductor substrate are made at the same position. An SIMS profile is calibrated by a method of least squares so that a dose amount determined from the SIMS profile coincide with a dose amount determined from the concentration profile of a carrier which is calculated from the pulse CV characteristics in a range where accuracy of the carrier concentration is secured. In the case where plural impurities are introduced, a measurement of pulse CV and SIMS measurement are made and the distribution of impurity concentration and the distribution of carrier concentration are estimated by simulation every time when an impurity is introduced. When an impurity is introduced in a high concentration, an impurity of the inverse conductive-type to that of the former impurity is introduced.

Abstract: A cellular mobile communication network in a code division multiple access system includes plural base stations covering cells, respectively, a host base station communicable with the plural base stations and plural mobile stations moved in the cells; when a mobile station becomes uncontrollable, the base station communicating the failure mobile station requests the host base station to register the identity code of the failure mobile station in a list of failure stations, and changes the control channel from an original radio frequency to a new radio frequency without informing the failure mobile station of the new radio frequency so as to disconnect the failure mobile station from the cellular mobile communication network; when another mobile station transmits a request for communication to a base station, the base station inquires the host base station whether the request is acceptable or not, and the host base station checks the list to see whether the identity code of the mobile station has been already

Abstract: A semiconductor memory device in an SRAM using a 4 transistor-type memory cell which device includes an error writing protection circuit for preventing any information from being written into a memory cell into which any information is not needed to be written owing to line capacitance between adjacent bit lines. The error writing protection circuit includes an N-type transistors, a P-type transistor, and diodes. Hereby, it is determined whether or not a bit line is charged with electricity in accordance with electric potential of an adjacent bit line, and there is not charged with electricity a bit line for which there is no possibility of any information from being written, but there is charged with electricity only bit lines where there is possibility of any information being written in error. Thus, there is flowed no excess current.

Abstract: A capacitor and a dynamic random access memory (DRAM) incorporating such a capacitor, includes a first layer of conducting, doped perovskite material, a second layer of another conducting, doped perovskite of opposite polarity in contact with the first layer, and a depletion layer formed at an interface between the first and second layers of conducting perovskite materials, the depletion layer being an insulating layer of the capacitor. Another capacitor and DRAM incorporating such a capacitor, includes a first electrode, a second electrode opposing the first electrode, and a thin-film of high dielectric constant perovskite material sandwiched between the first and second electrodes. At least one of the first and second electrodes is formed from substantially the same perovskite material, as the thin-film, in conducting, doped form.