Abstract: A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators adjacent P-wells, wherein the first divots have a greater depth than the second divots.

Abstract: A vehicle direction correcting apparatus comprises: a first filter for passing therethrough a low frequency component contained in the output voltage of a relative direction detecting unit to thereby produce a first output voltage; a second filter having delay time different from that of the first filter, for passing therethrough a low frequency component contained in the output voltage of the relative direction detecting unit to thereby produce a second output voltage; a voltage judging unit for judging as to whether or not the first output voltage of the first filter is made coincident with the second output voltage of the second filter within a predetermined error range; and a control unit for setting an output voltage of the relative direction detecting unit as the central point potential in the case that the voltage judging unit judges that the first output voltage is made coincident with the second output voltage within the predetermined error range.

Abstract: An over-sampling type clock recovery circuit includes a phase difference detecting section (TIPD, CP, LFP), a phase adjusting section (VCO, VD, FD) and a signal selecting section (LDEC, SW). The phase difference detecting section (TIPD, CP, LFP) detects a phase difference between a data signal and each of a plurality of active sets of clock signals, and generates a phase adjustment signal from a plurality of phase difference data corresponding to the detected phase differences. The phase adjusting section (VCO, VD, FD) generates N (N is an integer equal to or larger than 2) sets of clock signals and adjusts phases of clock signals of the N sets based on the phase adjustment signal. The signal selecting section (LDEC, SW) selects a part or all of the N sets of clock signals based on the detected phase differences from the phase difference detecting section. The selected sets of clock signals are supplied to the phase difference detecting section as the plurality of active sets of clock signals.

Abstract: In a method for manufacturing a bipolar transistor, a first insulating layer, a first polycrystalline silicon layer of a second conductivity type, and a second insulating layer are sequentially formed on a semiconductor substrate of a first conductivity type. Then, the second insulating layer and the first polycrystalline silicon layer are patterned to form an opening therein. Then, the first insulating layer is over etched by using the second insulating layer and the first polycrystalline silicon layer as a mask. Then, a second polycrystalline silicon layer is formed on the entire surface. Then, an oxidizing process is performed upon the second polycrystalline silicon layer except for a part of the second polycrystalline silicon layer under the first polycrystalline silicon layer, and the oxidized part of the second polycrystalline silicon layer is removed by a wet etching process. Then, impurities of the second conductivity type are implanted into the semiconductor substrate to form a base region.

Abstract: A photo-resist mask is removed from an inter-level insulating structure by using plasma produced from N.sub.x H.sub.y gas, and the plasma does not make an organic insulating layer forming part of the inter-level insulating structure hygroscopic, because SiCH.sub.3 bond is never replaced with Si--OH bond during the removal of the photo-resist mask.

Abstract: To obtain a small contact-less memory device, a memory device includes a semiconductor chip having a first surface and a second surface located at a level lower than that of the first surface, a memory cell array formed on the second surface, a peripheral circuit, for operating the memory cell array, formed on the first surface, and a connecting portion, for electrically connecting the memory cell array to the peripheral circuit, formed on the first surface.

Abstract: A thin Co--Fe--Ni magnetic film comprising from 40% to 70% by weight of cobalt, from 20% to 40% by weight of iron, and from 10% to 20% of nickel, and having a crystal structure of a mixed crystal with an .alpha. phase of a body-centered cubic structure and a .gamma. phase of a face-centered cubic structure.

Abstract: A device includes first and second contacts formed on a channel material, a film of doped first insulator material interposed between the first and second contacts, and a second insulator material interfaced with the doped first insulator material with an area of said channel material therebetween. The second insulator material is doped so as to have carriers of opposite charge to those in the channel material.

Abstract: To provide an input circuit of an IC wherein the current flowing towards the input terminal when receiving a LOW level signal can be restricted to minimum, and the input threshold level can be controlled appropriately without degrading transition performance of the input circuit, an input circuit includes: a current control means for controlling a first current to be supplied to a first node according to a second current to be supplied to a second node an input level transfer means for transferring logic of the external logical signal into an intermediate signal whereof potential of a HIGH level is restricted within a power supply voltage; a level shift means for shifting a LOW level of the intermediate signal to substantially the same level of a LOW level of the external logical signal; an inverter for outputting a signal of low output impedance by inverting the shifted intermediate signal; and a transition current generating means for controlling the level shift means to supply a sufficient transition curre

Abstract: A disk drive system, includes an arm for mounting a head, and at least one component, coupled to the arm, for being synchronized to maintain a zero net angular momentum of the arm and the at least one component. Another disk drive system including a read/write head, includes a torque counter-generating member for being synchronized to maintain a zero net angular momentum of the head.

Abstract: A portable terminal apparatus including a main body with display unit capable of displaying a character or other patterns on an upper surface side thereof and a key display on a lower surface side thereof, and a lid which can be mounted on and detached from the main body and which has a transparent touch panel arranged at a position to cover either one of the display means and the key display when the lid is mounted on the main body.

Abstract: In an emitter follower circuit, a bipolar transistor is connected to a resistor element. The bipolar transistor has a temperature dependent characteristic. A current source circuit is connected to the resistor element to flow a current through the resistor element such that a voltage drop by the resistor element has an opposite temperature dependent characteristic to the first temperature dependent characteristic of the bipolar transistor.

Abstract: An installation structure for a writing instrument includes an outer cylinder and a lead advancing mechanism, which is housed in the outer cylinder and has a sleeve provided with a protruding portion protruding in the outward direction, for advancing a lead by a predetermined amount. The lead advancing mechanism is installed in the outer cylinder so as to prevent the lead advancing mechanism from coming off (e.g., decoupling from) the outer cylinder by making the front end of the sleeve abut a step portion formed on the inner peripheral surface of the outer cylinder and fixing the protruding portion provided on the sleeve to a second step portion formed on the inner peripheral surface of the outer cylinder.

Abstract: In order to form a film of organic-inorganic hybrid material, such as a perovskite material, in a selected stoichiometric ratio upon a surface of a substrate, the proposed method entails a number of simple steps. First, a substrate and a selected quantity of an organic-inorganic hybrid material are placed in a chamber, with the hybrid material being placed on a heater. Then, the hybrid material is heated sufficiently, as by passing an electric current through the heater, to cause its total ablation. As a consequence, a film of the organic-inorganic hybrid material, in the aforesaid selected stoichiometric ratio, reassembles as a film upon a surface of the substrate. During the heating step, the chamber may be either evacuated to a pressure below 10.sup.-3 torr or filled with an inert gas, such as nitrogen.

Abstract: A display device is provided with a center unit 10 having a center display unit 12, a slave unit 20 having a slave display unit 21 and a communication line for communicatively connecting the center unit 10 and the slave unit 20. When the center control microcomputer 15 of the center unit 10 detects a predetermined operation through a key operating unit 14, the center control microcomputer 15 and the slave control microcomputer 24 make two of the center display unit 12 and the slave display unit 21 provide a linking display as if these display units operate as one display unit.

Abstract: Disclosed is a switching circuit which has: at least one unit circuit connected in series, the unit circuit being composed of two field-effect transistors connected in series and an inductor that has one end connected to a connection point between the two field-effect transistors and another end grounded; wherein the gates of the two field-effect transistors are commonly connected and a bias voltage to control the turning on/off of the two field-effect transistors is equally applied through a resistance to the respective gates.

Abstract: A memory control system comprises a main memory including a plurality of banks; two or more requesters each of which includes an MPU or an I/O section which outputs a request that is addressed to a bank of the main memory; and a pipeline-controlled system bus connecting the main memory and each requester. Each requester includes a request sending control circuit, a system bus arbitration circuit, and a bank busy management section. The request sending control circuit which received a request from the MPU or the I/O section executes a system bus acquisition request to the system bus arbitration circuit of the requester and other requesters after confirming that the bank to which the request has been addressed is not busy for the request by referring to the bank busy management section.

Abstract: A semiconductor package which can prevent peeling of outer leads from solder caused by thermal expansion and contraction, after the semiconductor package is mounted on a printed wiring board, is disclosed. The semiconductor package according to this invention includes a resin sealed body having a semiconductor chip sealed therein and outer leads led out of the resin sealed body. The outer lead has a first and second inflection parts, and the outer lead includes a first portion which defines the segment from a lead-out part of the outer lead in the resin sealed body to the first inflection part, a second portion which defines the segment from the first inflection part to the second inflection part, and a third portion which defines the segment from the second inflection part to a terminating part of the outer lead. The length of the first portion is larger than the length of the third portion.

Abstract: A method of performing overlapping operations with a memory device may have a sense amplifier circuit and two drivers connected to the sense amplifier circuit. Two data bus lines may be connected to the sense amplifier circuit to receive data signals. The method may include applying a first equalize signal and second equalize signal to the sense amplifier circuit to allow the sense amplifier circuit to receive the data signals across the data bus lines, applying a switch signal to the sense amplifier circuit to connect the data bus lines to a read data bus, and changing a state of the first equalize signal such that the data bus lines either receive new data or the data bus lines are equalized to a predetermined voltage while the data is on the read data bus and is capable of being read.