Patents Represented by Attorney McGinn & Gibb, PLLC
  • Patent number: 6894651
    Abstract: A built-in antenna for being installed in a housing of insulating material has a metal plate that has a radiating portion and a feeder terminal. The radiating portion has a plurality of penetrating holes to be fitted to a plurality of protrusions provided on the housing side, and a plate spring that is formed extending from an edge of each of the plurality of penetrating holes to the center of the each of the plurality of penetrating holes.
    Type: Grant
    Filed: December 9, 2003
    Date of Patent: May 17, 2005
    Assignees: Hitachi Cable, Ltd., Toshiba Corporation
    Inventors: Toshiyuki Yokochi, Shinichi Takaba, Takahiro Sugiyama
  • Patent number: 6894317
    Abstract: A semiconductor element including an electrically insulating substrate, semiconductor layers including first and second semiconductor layers of different conduction types and formed on the electrically insulating substrate, a first electrode formed on the first semiconductor layer, and a second electrode formed on the second semiconductor layer revealed by etching at least the first semiconductor layer, wherein a die-bonding electrode is formed on a side surface of the second electrode, on a side surface of the second semiconductor layer and on a region of from a side surface to a bottom surface of the electrically insulating substrate. Metal-metal contact is formed between the die-bonding electrode and the side surface of the second electrode, so that low-resistance contact is obtained here.
    Type: Grant
    Filed: June 11, 2002
    Date of Patent: May 17, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Naoki Nakajo
  • Patent number: 6893064
    Abstract: A front portion of an under cover fastened to a cross member extends to the front, so that the extension is formed as a mounting bracket for a bumper face. A lower impact absorbing member is integrally formed on the bracket which lower impact absorbing member has a rib provided to erect from the bracket in such a manner as to be opposed to an inner vertical surface of a lower protruding portion of the bumper face and a plurality of beads disposed behind the rib for transmitting an impact from the rib to the cross member, to thereby provide a bumper structure with appropriate impact absorbing function at a lower portion thereof, with a simple structure and without increasing the number of components.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: May 17, 2005
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Kenichi Satou
  • Patent number: 6893945
    Abstract: An Al0.15Ga0.85N layer 2 is formed on a silicon substrate 1 in a striped or grid pattern. A GaN layer 3 is formed in regions A where the substrate 1 is exposed and in regions B which are defined above the layer 2. At this time, the GaN layer grows epitaxially and three-dimensionally (not only in a vertical direction but also in a lateral direction) on the Al0.15Ga0.85N layer 2. Since the GaN layer grows epitaxially in the lateral direction as well, a GaN compound semiconductor having a greatly reduced number of dislocations is obtained in lateral growth regions (regions A where the substrate 1 is exposed).
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: May 17, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Norikatsu Koide
  • Patent number: 6894338
    Abstract: A data storage element (and method of forming the same) includes a substrate comprising a semiconductor material, a metal oxide layer including an electrically insulating rare earth metal oxide disposed upon a surface of the substrate, a conductive material disposed upon the metal oxide layer, a first electrode electrically connected to the conductive material, and a second electrode connected to the substrate.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: May 17, 2005
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Jr., Eduard Albert Cartier, Supratik Guha
  • Patent number: 6894734
    Abstract: A liquid-crystal display device is provided wherein large electrostatic capacitance can be obtained without exposure of a metal film on a surface of a TFT array substrate, and yield in production and stability in images are improved. In the liquid-crystal display device of the present invention, a thin-film transistor section is mounted which is used to selectively connect either of a data wiring formed on a gate insulating film or a transparent electrode by a gate connected to an address wiring placed in each of picture element areas. In each of picture element areas, a capacitor section is formed with a first electrode formed, on the gate insulating film, using the same conductive film as used for the data wiring and a second electrode formed, on an upper layer insulating film formed on the gate insulating film, using the same transparent conductive film as used for a transparent electrode.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: May 17, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Hirofumi Ihara
  • Patent number: 6895183
    Abstract: An optical wavelength division coupler 11 wavelength-divides a wavelength multiplexed light to respective wavelength lights each of which is dropped to an optical gate switch 15-i (i=1˜n) and a light receiver 13-i by an optical coupler 12-i and supplied to an optical light fault monitor 14 through the light receiver 13-i. When the optical signal deterioration monitor 14 detects an optical loss of wavelength (OLOW), an optical loss of signal (OLOS) or an optical signal degrade (OSD) in wavelength lights processed by the optical coupler 12-i as a fault detection signal in an optical layer, a controller 19 controls the optical gate switch 15-i to cut off wavelength light passing therethrough and sends an optical alarm indication signal (AIS-O) to a downstream side. Therefore, when a loss of signal is detected by the light receiver 13-i, the optical signal deterioration monitor 14 can know the alarm indication signal (AIS) from the upstream side, removing the necessity of special hardware therefor.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: May 17, 2005
    Assignee: NEC Corporation
    Inventors: Hirofumi Shimomura, Naoya Henmi, Hitoshi Takeshita
  • Patent number: 6890087
    Abstract: A relatively small-diameter aperture fluorescent lamp is manufactured easily with high yield and at low cost. An aperture portion is formed in a manner that a thread-like member is inserted into a glass tube having an ultraviolet ray reflection layer and a phosphor layer formed on its inner surface, the glass tube is bent in a predetermined shape by using a bending jig, the thread-like member is pressed to the phosphor layer formed in a predetermined region in the bending member side of the glass tube while both ends thereof are pulled tight, the thread-like member is reciprocated, and phosphor of the phosphor layer in this region is exfoliated.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: May 10, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Shin-Ichirou Ono
  • Patent number: 6890864
    Abstract: There are provided a semiconductor device fabricating method for forming a wiring layer on a semiconductor substrate, followed by cleaning, which may prevent elution and oxidation of the wiring layer, and a treating liquid used in the fabricating method. A Cu wiring, an interlayer film over the Cu wiring and an opening in the interlyaer film to expose the surface of the Cu wiring are formed in a plasma atmosphere. IPA is sprayed to the semiconductor device, and then, an organic release process is performed thereto with an amine solvent to remove an etching residue. The semiconductor device is rinsed with the IPA again to remove the remaining amine, and then is cleaned with a treating liquid, which is alkalescent. Then, it is rinsed with pure water or CO2 water and is dried.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: May 10, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Kenichi Nakabeppu, Hiroaki Tomimori, Toshiyuki Takewaki, Nobuo Hironaga, Hiroyuki Kunishima
  • Patent number: 6891203
    Abstract: According to the invention, a Group III nitride compound semiconductor light-emitting element is provided with a light-emitting layer comprising two layers of different in ratio of AlGaInN composition, and emitting light with an emission peak wavelength in an ultraviolet region and light with an emission peak wavelength in a visible region. The light-emitting element and a fluorescent material excited by light in the ultraviolet region are combined to configure a light emitting device.
    Type: Grant
    Filed: January 4, 2002
    Date of Patent: May 10, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takahiro Kozawa, Naoki Shibata
  • Patent number: 6891228
    Abstract: A method and structure for a CMOS device comprises depositing a silicon over insulator (SOI) wafer over a buried oxide (BOX) substrate, wherein the SOI wafer has a predetermined thickness; forming a gate dielectric over the SOI wafer, forming a shallow trench isolation (STI) region over the BOX substrate, wherein the STI region is configured to have a generally rounded corner; forming a gate structure over the gate dielectric; depositing an implant layer over the SOI wafer; performing one of N-type and P-type dopant implantations in the SOI wafer and the implant layer; and hearing the device to form source and drain regions from the implant layer and the SOI wafer, wherein the source and drain regions have a thickness greater than the predetermined thickness of the SOI wafer, wherein the gate dielectric is positioned lower than the STI region.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: Heemyong Park, Byoung H. Lee, Paul D. Agnello, Dominic J. Schepis, Ghavam G. Shahidi
  • Patent number: 6889643
    Abstract: A gap (34) for forming an excess thickness portion is provided between a pair of first dies (26, 27) and a intermediate portion (32) of the second die (24), and an excess thickness portion (35) is formed in bottom portions of the valve guide walls (28, 29) of valve guide walls.
    Type: Grant
    Filed: June 25, 2003
    Date of Patent: May 10, 2005
    Assignee: Koyo Seiko Co., Ltd.
    Inventor: Nobutsuna Motohashi
  • Patent number: 6891196
    Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode is isolated in each layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer and a TFF area. A drain electrode layer is formed by a first passivation film with the first passivation film formed as an upper layer. In a second passivation film, formed above the first passivation film, are bored a first opening through the first and second passivation films and a second opening through the second passivation film. A wiring connection layer is formed by ITO provided as an uppermost layer.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: May 10, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
  • Patent number: 6891231
    Abstract: A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electrode. The insulating material can be provided either as a layer or distributed within a gate dielectric material disposed under the gate electrode.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: May 10, 2005
    Assignee: International Business Machines Corporation
    Inventors: Nestor Alexander Bojarczuk, Jr., Kevin Kok Chan, Christopher Peter D'Emic, Evgeni Gousev, Supratik Guha, Paul C. Jamison, Lars-Ake Ragnarsson
  • Patent number: 6889456
    Abstract: An LED light source is received in a groove portion provided in a light guide plate. The groove portion is covered with a base member, and the circumferential edge of the base member is bonded to the light guide plate. Concave portions or convex portions having desired shapes are provided in a surface opposite to a light emission observable surface of the light guide plate so as to form character portions.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: May 10, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Minoru Shibata, Osamu Yamanaka, Masanobu Muto
  • Patent number: 6890589
    Abstract: Into a mixture solution 2 of a high-refractive-index photo-curable resin A and a low-refractive-index photo-curable resin B, light capable of curing only the resin A is led through an optical fiber 1 so that a cured resin 211 of the resin A having a diameter substantially equal to the diameter of a core portion of the optical fiber is formed so as to extend from a tip of the optical fiber. Then, the residual mixture solution 2 is cured. In this manner, a module having the previously cured high-refractive-index resin 211 as an optical waveguide can be formed easily. On this occasion, the mixed state of the mixture solution 2 can be kept good enough to facilitate the formation of the high-refractive-index resin 211 when the solubility parameter ?A of the high-refractive-index photo-curable resin A and the solubility parameter ?B and volume fraction ?B of the low-refractive-index photo-curable resin B satisfy the following expression (4). |?A??B|<?7.5?B+6.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: May 10, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yukitoshi Inui, Kuniyoshi Kondo, Tatsuya Yamashita, Akari Kawasaki, Manabu Kagami, Hiroshi Ito, Shin Sato, Eiichi Okazaki
  • Patent number: 6892072
    Abstract: A method of optimizing the search for cells in a mobile telecommunication network comprising a plurality of cells, each cell accommodating one base station exchanging synchronization data with a mobile device UE via a channel SCH, so as to allow subscribers' mobile devices to perform measurements on at least one cell adjacent to the current cell for retrieving a scrambling code specific to the adjacent cell. The method has a step of applying a digital filtering to measurement samples collected in a plurality of time windows so as to give a major weight to measurements performed in the most recent time windows.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: May 10, 2005
    Assignee: NEC Corporation
    Inventor: Lionel Hayoun
  • Patent number: 6889102
    Abstract: A bug collection apparatus for use when a design modification is made to a bug in a drawing designed by using a computer aided design system, the apparatus formed by a first means for detecting whether the modification to the bug exceeds a pre-established criterion, and a second means for collecting and recording a bug information corresponding to the modification when the first means detecting that the modification exceeds the pre-established criterion.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: May 3, 2005
    Assignee: NEC Corporation
    Inventor: Takumi Hasegawa
  • Patent number: 6886962
    Abstract: In a shielded reflective LED, each of light sources can be surface-mounted substantially without being influenced by heat distortion based on the difference in thermal expansion coefficient between resin and metal because the light source is so small-sized that only one light-emitting element is sealed with a resin. Moreover, variations in luminous intensity and chromaticity of each of light-emitting elements used in three-color light sources can be examined in advance. Hence, well-matched three-color light sources can be mounted in combination so that display unevenness of a full color display can be reduced greatly. Further, the surface of the substrate portion on which the light source is fixed is silk-screen-printed in black. Hence, external light which enters the device through the optical opening portion when the device is turned off is reflected by the reflecting mirror and absorbed to the surface of the substrate portion.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: May 3, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yoshinobu Suehiro
  • Patent number: 6888221
    Abstract: A method and structure for a bipolar transistor comprising a patterned isolation region formed below an upper surface of a semiconductor substrate and a single crystal extrinsic base formed on an upper surface of the isolation region. The single crystal extrinsic base comprises a portion of the semiconductor substrate located between the upper surface of the isolation region and the upper surface of the semiconductor substrate. The bipolar transistor further comprises a single crystal intrinsic base, wherein a portion of the single crystal extrinsic base merges with a portion of the single crystal intrinsic base. The isolation region electrically isolates the extrinsic base from a collector. The intrinsic and extrinsic bases separate the collector from an emitter. The extrinsic base comprises epitaxially-grown silicon. The isolation region comprises an insulator, which comprises oxide, and the isolation region comprises any of a shallow trench isolation region and a deep trench isolation region.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: May 3, 2005
    Assignee: International Business Machines Corporation
    Inventors: Alvin J. Joseph, Qizhi Liu, Devendra K. Sadana