Abstract: An electric power steering apparatus having a steering system capable of flexibly setting a relationship between a steering angle of a steering wheel and a wheel angle of a tire. The first motor controls steering reaction force exerted on the steering wheel. The on-center region determination section determines whether the steering wheel is in a position of an on-center region. The tire reaction force torque detection section detects tire reaction force torque transferred from the tire. The control section calculates a steering torque based on the tire reaction force torque and a torque gain. This torque is detected by the tire reaction force torque detection section. And the control section controls the first motor to exert the steering reaction force corresponding to the above calculated steering torque on the steering wheel. This control section also sets the torque gain in case of determining of on-center region larger than that in case of determining of non-on-center region.

Abstract: A method and structure for a single or dual damascene interconnect structure comprises forming wiring lines in a metallization layer over a substrate, shaping a laminated insulator stack above the metallization layer, patterning a hardmask over the laminated insulator stack, forming troughs in the hardmask, patterning the laminated insulator stack, forming vias in the patterned laminated insulator stack, creating sidewall spacers in the bottom portion of the vias, depositing an anti-reflective coating on the sidewall spacers, etching the troughs, removing the anti-reflective coating, depositing a metal layer in the troughs, vias, and sidewall spacers, and applying conductive material in the troughs and the vias. The laminated insulator stack comprises a dielectric layer further comprising oxide and polyarylene.

Abstract: An LED lamp apparatus comprises LED, a circuit member, and a case member. The case member has an LED seat for holding the LED. The circuit member has metal plates embedded in the case member. The metal plates have LED connection members exposed from the case member. The LED connection members have been resistance welded respectively to leads of the LED.

Abstract: In a lateral electric field liquid crystal display device, a major electrode portion for generating a lateral electric field is formed using a layer different from a layer on which other electrodes and lines are formed. In this case, the major portion is formed to have a thickness of {fraction (1/20)} to ? of the thickness of each of the other electrodes and lines. Thus, flatness of a base film of an alignment layer is significantly improved, also alignment layer material can be coated and formed with high flatness on the base film, and rubbing of the alignment layer material can be performed uniformly for the overall substrate surface.

Abstract: Disclosed is a method and structure for forming a split-gate fin-type field effect transistor (FinFET). The invention produces a split-gate fin-type field effect transistor (FinFET) that has parallel fin structures. Each of the fin structures has a source region at one end, a drain region at the other end, and a channel region in the middle portion. Back gate conductors are positioned between channel regions of alternating pairs of the fin structures and front gate conductors are positioned between channel regions of opposite alternating pairs of the fin structures. Thus, the back gate conductors and the front gate conductors are alternatively interdigitated between channel regions of the fin structures.

Abstract: An arrayed waveguide element having flat optical frequency characteristics, and an optical communication system using such arrayed waveguide element are realized by providing the arrayed waveguide element that is prepared by forming an inputting channel waveguide as well as an outputting channel waveguide, a channel waveguide array, a first sector form slab waveguide for connecting the inputting channel waveguide with the channel waveguide array, and a second sector form slab waveguide for connecting the outputting channel waveguide with the channel waveguide array on a substrate. A waveguide part wherein the outputting channel waveguide is connected with the second sector form slab waveguide is defined in a parabolic configuration, whereby flat optical frequency characteristics are realized. Furthermore, it is possible that an individual parabolic configuration is adjusted in response to a wavelength, so that it can cope with a trend of broad band in optical signals.

Abstract: A bit rate converter capable of avoiding slip of data in a memory for use in bit rate adjustment is disclosed. A phase comparator compares a write address and a read address of the memory to produce a phase difference. The write address is ahead of the read address in the memory. A stuffing rate controller selects one of a plurality of preset fixed stuffing rates depending on the phase difference. A stuff pulse inserter inserts a stuff pulse into readout data from the memory at the selected stuffing rate. When normally operating, a normal fixed stuffing rate is selected. When the phase difference is small than a lowest threshold value, a higher fixed stuffing rate is selected. When the phase difference is greater than a highest threshold value, a lower fixed stuffing rate is selected.

Abstract: In a network that roughly comprises a temporary master station and a plurality of slave stations and is an adhoc network, which can be immediately constructed in situ, and is a temporary master station interposition-type network in which a temporary master station is present, the temporary master station receives and judges an interference detection packet sent from the slave station. By virtue of this construction, an asynchronous interference avoiding method and an asynchronous interference avoiding system can be realized which can reliably avoid interference.

Abstract: An electric power steering device capable of attaining the expected control and control characteristics while using a phase compensator, includes a target current setting unit including a compensation unit having an inertia compensating unit for outputting an inertial compensating current value and a damper control unit for outputting a damper control current value, a compensation unit for outputting a compensation current value, a basic assist current setting unit for outputting a basic assist current value, and a phase compensating unit connected with the downstream stage of the basic assist current setting unit for outputting a target current value by performing a phase compensation of an added current value while receiving no influence from the dead zone or the characteristic break points of an assist table for setting the basic assist current value.

Abstract: A waveguide device has an input waveguide, a plurality of output waveguides, a channel waveguide array, an input slab waveguide, and an output slab waveguide. The output slab waveguide connects an output end of the channel waveguide array to the output waveguide, and has optical input/output characteristics set to given ratios for the output waveguides with respect to the input waveguides. The waveguide device is capable of adjusting signal levels output from the respective waveguides without the need for circuit parts for compensating for loss differences and also the need for a process of highly accurately attaching parts.

Abstract: A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

Abstract: Each of a plurality of driving circuits constituting a constant current driving apparatus is composed of a first current mirror circuit and a second current mirror circuit. The first current mirror circuit outputs a plurality of output currents, each of which corresponds to a reference current. Accordingly, the variation in the output current can be reduced between the driving circuits adjacent to each other.

Abstract: A layer comprising silicon oxide (SiO2) is formed on (111) plane of a silicon (Si) substrate in a striped pattern which is longer in the [1-10] axis direction perpendicular to the [110] axis direction. Then a group III nitride compound semiconductor represented by a general formula AlxGayIn1?x?yN (0?x?1, 0?y?1, 0?x+y?1) is laminated thereon. The group III nitride compound semiconductor represented by a general formula AlxGayIn1?x?yN (0?x?1, 0?y?1, 0?x+y?1) grows epitaxially on the substrate-exposed regions B which are not covered by the SiO2 layer, and grows epitaxially on the SiO2 layer in lateral direction from the regions B. Consequently, a group III nitride compound semiconductor having no dislocations can be obtained.

Abstract: A method (and system) for compressing an extensible markup language (XML) document, includes compressing an XML document such that information in a markup portion therein is maintained in a compressed form to allow the document to be reconstructed. During the compressing, the markup portion and a non-markup portion of the document are separated, and the non-markup component is compressed using a first compression method and the markup component is compressed using a second compression method.

Abstract: A method and structure is disclosed for serially storing and retrieving fuse information to and from a non-scannable static random access memory (SRAM) array within an embedded DRAM structure. The SRAM array is part of a scan chain and is connected to upstream and downstream latches that make up the scan chain. Various data is serially scanned into the scan chain. As the data flows through the entire scan chain, the invention counts the number of bits scanned into the embedded DRAM structure using a counter. The counter can be included within the embedded DRAM structure. After the counter counts to an amount equal to the number of bits of storage of all downstream scan latches in the scan chain, the invention loads the fuse information into a shift register. When the shift register is full, the invention loads the contents of the shift register to a SRAM line. The lengths of the shift register and the SRAM line are equal to a fuse word.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: A liquid-crystal lens includes a hologram liquid-crystal element having a liquid crystal which provides a light beam transmitting therethrough with a phase change so as to have a wavefront of a blaze-hologram shape; and a segment liquid-crystal element including a first electrode divided correspondingly to the blaze-hologram shape, a second electrode opposed to the first electrode and a liquid crystal for providing the transmitting light beam with a phase change by voltage application to the first and second electrodes, the segment liquid-crystal element being arranged coaxial to the hologram liquid-crystal element.

Abstract: A thin type printed circuit board with an enclosed capacitor of a large capacitance. The printed circuit board includes metal sheet 11 having roughed surface presenting micro-irregularities, a dielectric film for capacitor 12 covering the surface of the metal sheet, and a first electrically conductive layer of electrically conductive resin 13 covering the surface of the dielectric film. A second electrically conductive layer 14 is provided on the surface of the first electrically conductive layer in a region of via for cathode side connection 18. The metal sheet and the first and second electrically conductive layers are encapsulated by resin 15. The via for cathode side connection 18, obtained on boring through the resin 15 until reaching the second electrically conductive layer 14, is coated with an electrode 20. A via for anode side connection 19 obtained on boring through the resin 15 is coated with an electrode 21 that is insulated from the second electrically conductive layer 13 by the resin 15.

Abstract: A method and structure for forming a refractory metal liner, includes depositing a layer of refractory metal on a first conductive layer, at least half of the depositing being carried out in the presence of an amount of passivating agent that is sufficient to impede subsequent reaction of at least a top half of the layer of refractory metal with the first conductive layer and is less than an amount of passivating agent necessary to form a stoichiometric refractory metal with the passivating agent, and annealing the refractory metal and the first conductive layer in a first element ambient, thereby forming a stoichiometric refractory metal with the first element in at least a portion of the top half of the layer of refractory metal.

Abstract: Application execution contexts within an untrusted computer system are classified as trusted or untrusted based on respective names assigned to the execution contexts. If an application runs in an untrusted execution context, an operating system within the untrusted computer system prevents the application from initiating a connection with a trusted computer system and accessing sensitive parts of the untrusted computer system. If the application runs in a trusted execution context, the operating system permits the application to initiate a connection with the trusted computer system.