Patents Represented by Attorney McGinn & Gibb, PLLC
  • Patent number: 6943379
    Abstract: In a light emitting diode, a blue light emitting element is mounted on a base having a cup through a phosphor-containing mount so that the light emitting element is located within the cup and is mounted on the bottom of the cup through the phosphor-containing mount. The light emitting diode includes a light emitting element and a p electrode. By virtue of the above construction, blue light emitted from the light emitting element can be reflected from the lower surface of the p electrode without being radiated directly from the upper surface of the light emitting element to the outside of the light emitting diode. As a result, the blue light emitted from the light emitting element can be efficiently mixed with yellow light given off from the phosphor in the phosphor-containing mount to provide white light which is radiated to the outside of the light emitting diode with high efficiency.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: September 13, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yoshinobu Suehiro, Hitomi Kawano, Tatsuya Takashima, Yuji Takahashi, Atsuo Hirano
  • Patent number: 6944217
    Abstract: A non-recursive filter for receiving samples and generating a filtered signal, the filter comprises a plurality of successive partial summation units, each partial summation unit having multiplier for multiplying an undelayed state of each of the samples, and an adder for adding multiplied samples; and a plurality of delay elements each coupled to the adder for receiving added samples and for providing a delayed output of the added samples to a successive partial summation unit.
    Type: Grant
    Filed: February 1, 2000
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventor: Brian L. Allen
  • Patent number: 6943894
    Abstract: A laser distance measuring system has a simple optical structure with which abnormal return light can be removed. The laser distance measuring system includes a laser light source that generates at least two interferable light beams with different frequencies on a same optical axis, a parallel reflecting portion that includes a reflecting surface, which is included in an object that moves along a measurement axis and that is arranged on the measurement axis, and returns an incident light beam in a direction opposite that at which it is incident and at a certain spacing from and parallel to the incident light beam, and an interferometer that is positioned between the laser light source and the parallel reflecting portion and that is arranged on the measurement axis. The optical axes of the light beams are displaced parallel to one another from the measurement axis and one of the light beams is passed through the interferometer and guided to the parallel reflecting portion.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: September 13, 2005
    Assignee: Pioneer Corporation
    Inventor: Hiroaki Kitahara
  • Patent number: 6942060
    Abstract: A portable information terminal device has a plurality of casings providing a front surface and a rear surface, respectively. The casings have walls defining spaces in which speakers are housed and thicker than walls thereof that define a space in which a component including an internal circuit is housed. The walls defining the spaces in which speakers are housed are prevented from causing resonance due to vibrations of the speakers. The walls that define the space in which the component including the internal circuit is housed may be of a minimum thickness required irrespective of resonance caused by vibrations of the speakers. With the above arrangement, the portable information terminal device is small in size and weight.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: September 13, 2005
    Assignee: NEC Corporation
    Inventors: Atsuko Sugiura, Naoya Ishii, Makoto Nemoto
  • Patent number: 6943380
    Abstract: The light emitting device has a light emitting diode which is made of a nitride semiconductor and a phosphor which absorbs a part of lights emitted from the light emitting diode and emits different lights with wavelengths other than those of the absorbed lights. The phosphor is made of alkaline earth metal silicate fluorescent material activated with europium.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: September 13, 2005
    Assignees: Toyoda Gosei Co., Ltd., Tridonic Optoelectronics GmbH, Litec GBR, Leuchstoffwerk Breitungen GmbH
    Inventors: Koichi Ota, Atsuo Hirano, Akihito Ota, Stefan Tasch, Peter Pachler, Gundula Roth, Walter Tews, Wolfgang Kempfert, Detlef Starick
  • Patent number: 6944535
    Abstract: A map display apparatus and a map display method facilitate detection of the relationship between a destination position or a current position and the surrounding area, even when a detailed map is to be displayed on a narrow display area. A map display terminal displays a particular position, such as the destination position or the current position, on a map. The current position might be derived on the basis of position information from a Global positioning System. An initial display can be a wide area map having smaller scale than a detailed map and centered destination position or the current position. More detailed maps centered at that position are displayed in stages.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: September 13, 2005
    Assignee: NEC Corporation
    Inventor: Shinichiro Iwata
  • Patent number: 6943590
    Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: September 13, 2005
    Assignee: NEC Corporation
    Inventor: Takashi Kitahara
  • Patent number: 6942815
    Abstract: An ink jet recording head is capable of: preventing any of stagnation in ink flow, formation of vapor bubbles, cavitation, or like problems from occurring in the ink flow; realizing an excellent ink ejection operation, and thereby realizing a high quality gradation expression in recording; and, lessening a degree of a required accuracy both in dimension and in alignment of its components being stacked together. In a method for manufacturing the ink jet recording head provided with a pressure generating chamber, this chamber is constructed of a through-hole of a chamber plate and a pair of plates, between which plates the chamber plate is sandwiched.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: September 13, 2005
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Shigeru Umehara
  • Patent number: 6943405
    Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Andres Bryant, William F. Clark, Jr., David M. Fried, Mark D. Jaffe, Edward J. Nowak, John J. Pekarik, Christopher S. Putnam
  • Patent number: 6943584
    Abstract: A universal logic module of a programmable semiconductor device is constructed by first, second, third, fourth and fifth terminals, a first transfer gate connected between the first and fourth terminals, a second transfer gate connected between the second and fourth terminals, and an inverter connected between the third and fifth terminals. The first and second transfer gates are controlled by voltages at the third and fifth terminals, so that one of the first and second transfer gates is turned ON and the other of the first and second transfer gates is turned OFF.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: September 13, 2005
    Assignee: NEC Electronics Corporation
    Inventor: Tomonari Aoki
  • Patent number: 6943108
    Abstract: An interposer, located between an integrated circuit having power, ground and signal connections and a ceramic substrate having power, ground and signal connections, that includes an oxide layer formed on a polished surface of a silicon substrate, a thin film dielectric capacitor formed on the oxide layer, a plurality of metallized that electrically connect to either of the electrodes of the thin film dielectric capacitor, and vias than conduct power, ground and signals between a the ceramic substrate and the integrated circuit. The interposer connects the metallized vias to the integrated circuit by solder connections and also connects the vias conducting power, ground and signals from the ceramic substrate to the interposer by solder connections.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: September 13, 2005
    Assignee: International Business Machines Corporation
    Inventors: Mukta Ghate Farooq, John U. Knickerbocker, Srinivasa Reddy, Robert Anthony Rita
  • Patent number: 6943128
    Abstract: To lower the electrical resistance of a p-type semiconductor or the operation voltage of a light-emitting/light-receiving semiconductor device. An ion-plasma-type electron-beam irradiation apparatus 100 generates wide-area-radiation electron beams. The thus-generated electron beams are radiated to the outside through a thin metallic plate 108 formed on the outer surface of a beam extraction window 107. A p-type semiconductor is disposed below the beam extraction window 107 such that the p-type semiconductor is disposed about 20 mm away from the electron extraction window so as to be almost parallel to the metallic plate 108. When the surface of the p-type semiconductor is irradiated with electron beams by use of this apparatus, the electrical resistance of the p-type semiconductor can be effectively lowered within a short period of time; i.e., within about three minutes, which is considerably shorter than the time required in the case where a conventional electron-beam irradiation apparatus is employed.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: September 13, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Toshiaki Chiyo, Naoki Shibata
  • Patent number: 6938423
    Abstract: A method for conversion of heat in hot flue gases, vaporisation heat in the flue gases being released and converted into an energy carrier which converts from the liquid phase to gas phase.
    Type: Grant
    Filed: December 25, 2001
    Date of Patent: September 6, 2005
    Assignee: Addpower AB
    Inventor: Lennart Strand
  • Patent number: 6941354
    Abstract: There is provided a mobile terminal capable of properly selecting a communication network according to a kind of data targeted for sending and receiving when data is sent and received using a network. A mobile terminal 201 makes access to a WWW server 223 to acquire contents, and uses a packet communication gateway 225 to first acquire HTML data (main data) of the corresponding contents at the time of display. A tag for referring to various files (accompanying data) such as JPEG constructing the contents is embedded in this HTML data. Therefore, the mobile terminal 201 requests sizes of these files to the WWW server 223 by packet communication, and determines whether these files are acquired by packet communication or by line switching from the acquired file size. If these files are acquired by the line switching, the files are acquired from the WWW server 223 by using a line switching gateway 226 and making connection to an Internet network 222 through a public network 228, an Internet provider 229.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: September 6, 2005
    Assignee: NEC Corporation
    Inventor: Satoshi Odamura
  • Patent number: 6941528
    Abstract: The invention provides a method and structure for optimizing placement of redundant vias within an integrated circuit design. The invention first locates target vias by determining which vias do not have a redundant via. Then, the invention draws marker shapes on or adjacent to the target vias. The marker shapes are only drawn in a horizontal or vertical direction from each of the target vias. The invention simultaneously expands all of the marker shapes in the first direction to a predetermined length or until the marker shapes reach the limits of a ground rule. During the expanding, different marker shapes will be expanded to different lengths. The invention determines which of the marker shapes were expanded sufficiently to form a valid redundant via to produce a first set of potential redundant vias and the invention eliminates marker shapes that could not be expanded sufficiently to form a valid redundant via.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Robert J. Allen, Jason D. Hibbeler, Gustavo E. Tellez
  • Patent number: 6939733
    Abstract: A first group III nitride compound layer, which is formed on a substrate by a method not using metal organic compounds as raw materials, is heated in an atmosphere of a mixture gas containing a hydrogen or nitrogen gas and an ammonia gas, so that the crystallinity of a second group III nitride compound semiconductor layer formed on the first group III nitride compound layer is improved. When the first group III nitride compound layer is formed on a substrate by a sputtering method, the thickness of the first group III nitride compound layer is set to be in a range of from 50 ? to 3000 ?.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: September 6, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Naoki Shibata, Jun Ito, Toshiaki Chiyo, Shizuyo Asami, Hiroshi Watanabe, Masanobu Senda, Shinya Asami
  • Patent number: 6941356
    Abstract: A method and structure for a primary device adapted to communicate with secondary devices. The primary device has a central processing unit, a transceiver connected to the central processing unit which is adapted to transmit signals to and from the secondary devices and a user interface. The central processing unit automatically establishes communications with the secondary devices through the transceiver by sequentially (or in parallel) attempting communication with the secondary devices using a plurality of known communication protocols until communications are established, and the central processing unit changes the user interface depending upon which secondary devices are in communication with the primary device.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventor: Matthew Scott Meyerson
  • Patent number: 6940300
    Abstract: A device for use in a display system including an array of pixel cells formed on a substrate. Each pixel cell being coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines being formed on the substrate. The device includes first and second transistors formed on the substrate. Each transistor has a gate electrode and first and second electrodes defining a serpentine channel region there between voltage applied to the gate electrode controls conductivity of the channel region. Preferably, a common electrode includes one of the first and second electrodes of the first transistor and one of the first and second electrodes of the second transistor.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: September 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Leslie Charles Jenkins, Frank Robert Libsch, Michael Patrick Mastro, Robert Wayne Nywening, Robert John Polastre
  • Patent number: 6938705
    Abstract: A projected portion provided at a cylinder and projected in a radius direction is formed at an end face thereof on a side of a tool holding portion, and a holding portion on one side of holding portions for holding an outer periphery of the cylinder by at least two portions remote from each other in an axial direction to position in the radius direction of the cylinder is configured by a guide face having an inner diameter of a dimension substantially the same as an outer diameter of the projected portion and extended over to a contact face brought into contact with the projected portion from an end face of a cylinder case on a side of the tool holding portion.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 6, 2005
    Assignee: Hitachi Koki Co., Ltd.
    Inventor: Atsuyuki Kikuchi
  • Patent number: 6940839
    Abstract: The transmit power of a CDMA downlink channel is controlled from a base station by receiving a command signal from a mobile station requesting it to decrease the transmit power of the downlink channel. In response, the base station decreases the transmit power if a hypothetically decremented value of the transmit power is higher than a nominal lower limit of its power control range, and further decreases the transmit power if the downlink channel still has a quality higher than a specified value at the mobile station even when the hypothetically decremented value is lower than the nominal lower limit. The base station sets the transmit power equal to the nominal lower limit if the hypothetically decremented value is lower than the nominal lower limit and the downlink channel still has a quality higher than the specified value at the mobile station.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: September 6, 2005
    Assignee: NEC Corporation
    Inventor: Yukie Miyamoto