Patents Represented by Attorney McGinn Intellectual Property Law Group, PLLC
  • Patent number: 8222690
    Abstract: A semiconductor apparatus includes a doped semiconductor layer formed on a semiconductor substrate of a first conductivity type and first and second gate trenches formed in the semiconductor layer, the second gate trench being separated from the first gate trench in a first direction. The doped semiconductor layer includes a low concentration base region of a second conductivity typed formed between the first and second gate trenches, a first source region of the first conductivity type, a second source region of the first conductivity type, a first high concentration base region of the second conductivity type, and a second high concentration base region of the second conductivity type formed so that the first and second high concentration base regions are separated by the low concentration base region, and the second high concentration base region is not below both of the first and second source regions.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kinya Ohtani, Kenya Kobayashi
  • Patent number: 8223107
    Abstract: A data driver circuit includes a clock control circuit configured to generate a shift clock signal in synchronization to a clock signal; a shift register circuit having flip-flops in cascade-connection and configured to shift a pulse signal in synchronization with the shift clock signal, and a control circuit configured to receive a display data in response to the shifted pulse signal from the shift register circuit and to drive data lines of a display section based on display data to display the display data on the display section. The flip-flops are grouped in units of N (N is an integer of 2 or more) flip-flops into M (M is an integer of 2 or more) partial shift registers, and the shift register circuit is reset in units of partial shift registers.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuo Nakamura
  • Patent number: 8209301
    Abstract: A system (and method) of detecting an error in a database interaction, includes providing information about at least one of at least first and second software systems, and a mapping between at least a portion of the at least first and second software systems, and examining the at least one of the first and second software systems and the mapping to determine an error in an interaction between the at least first and second software systems.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: June 26, 2012
    Assignee: International Business Machines Corporation
    Inventors: Rajesh Bordawekar, Michael George Burke, Mukund Raghavachari, Oded Shmueli
  • Patent number: 8207761
    Abstract: A semiconductor device has: a pull-up circuit connectable to an internal terminal; a pull-down circuit connectable to the internal terminal; and an operation mode switch circuit. The operation mode switch circuit switches an operation mode based on a potential of the internal terminal when the pull-up circuit is connected to the internal terminal and a potential of the internal terminal when the pull-down circuit is connected to the internal terminal.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Kohamada
  • Patent number: 8208313
    Abstract: An SRAM includes a memory cell and a precharge circuit. The precharge circuit precharges a bit line pair with a power supply voltage before writing a data in the memory cell or before reading a data therefrom at a time of a normal mode, and which feeds a power supply voltage to at least a low level data-holding node of a node pair of the memory cell at a time of a read test mode, between time for writing a data in the memory cell and time for reading a data therefrom.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Kobatake
  • Patent number: 8209448
    Abstract: A data processing apparatus includes an arithmetic circuit and a peripheral device protection circuit that controls access of the arithmetic circuit to the peripheral devices. The peripheral device protection circuit has a first protection preset value and a second protection preset value set as a protection level higher than that of the first protection preset value. The peripheral device protection circuit includes: a setting selection circuit that generates access permission/denial information by referring to the first protection preset value and the second protection preset value when the arithmetic circuit operates at a first operation authority level, or by referring to the second protection preset value when the arithmetic circuit operates at the second operation authority level. An access protection circuit that determines permission/denial of access to the peripheral devices based on access information output from the arithmetic circuit and the access permission/denial information.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Junichi Sato, Hitoshi Suzuki
  • Patent number: 8209565
    Abstract: A data processing device includes a computing circuit that accesses a peripheral device connected to through a internal bus, an internal bus connection circuit that is provided between the computing circuit and the internal bus, and switches an enable and a disable state of an access from the computing circuit to the internal bus, an exception notification controller that outputs an exception occurrence notification signal to the computing circuit based on an error occurred in the peripheral device, and a bus disablement controller that instructs the internal bus connection circuit to disable an access from the computing circuit to the internal bus in accordance with the notification of the exception occurrence notification signal, and instructs the internal bus connection circuit to cancel the disablement of the access in accordance with a start of an exception processing based on the exception occurrence notification signal.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiko Akaike, Hitoshi Suzuki, Junichi Sato
  • Patent number: 8201525
    Abstract: A cooling device for an engine including a radiator circulation flow channel, a heater circulation flow channel, a bypass circulation flow channel, a valve, and a pump. The channels merge in the thermostat and form a common flow channel between the thermostat and the engine. The pump is provided in the common flow channel. At a start of a warm-up period and during the warm-up operation, circulation is substantially stopped by the thermostat, cooling water circulation is actuated in the bypass circulation flow channel, and an opening degree of the electronically controlled valve is gradually increased from a minimum as the cooling water temperature rises. The electronically controlled valve is not completely closed even when closed, and is open to a certain degree from an initial stage of the warm-up period, thereby causing part of the cooling water to flow in the bypass circulation flow channel.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: June 19, 2012
    Assignee: Yamada Manufacturing Co., Ltd.
    Inventors: Katsuyoshi Shiobara, Hidehiko Koyashiki
  • Patent number: 8202685
    Abstract: Lithography process is conducted to expose chip patterns to light on a semiconductor wafer. The process includes exposing a plurality of chip patterns to light in a first shot region in one direction on the semiconductor wafer, and exposing a plurality of chip patterns to light in a second region obtained by rotating the first shot region by 90° in a region in which all the chip patterns in the first shot region at the periphery of the semiconductor wafer are regarded as ineffective.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takanori Yamamoto
  • Patent number: 8200982
    Abstract: A method of processing semiotic data includes receiving semiotic data including at least one data set P, selecting a function h, and for at least one of each data set P to be collected, computing h(P), destroying data set P, and storing h(P) in a database, wherein data set P cannot be extracted from h(P). The method further includes selecting a private key/public key (K, k) once for all cases, one of destroying the private key K and sending the private key K to a trusted party, and choosing function h as the public encryption function corresponding to k.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Andrea Califano, Stephen Carl Kaufman, Marco Martens, William Robert Pulleyblank, Gustavo Alejandro Stolovitzky, Charles Philippe Tresser, Chai Wah Wu
  • Patent number: 8196436
    Abstract: Provided are a manufacturing method of an optical fiber base material and an optical fiber base material manufactured in the manufacturing method, the manufacturing method including: a process of combining at least two core base materials 70 by fusion-bonding to produce a single core base material; a process of fusion-bonding a pair of dummy glass rods 61 and 62 at both ends of the core base material 70 to produce a starting glass rod; a process of depositing, at an outer surface of the starting glass rod, glass particles generated by flame hydrolysis, to produce a porous base material 80; and a process of sintering and vitrifying, into transparent glass, the porous base material 80, to produce an optical fiber base material 310 that includes a core portion and a clad portion.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: June 12, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Mitsuo Saitou, Koichi Shiomoto, Mitsuji Sato, Shoji Hoshino, Seiya Yamada, Hiroshi Kato, Naomichi Osada
  • Patent number: 8200492
    Abstract: A method of updating an application in a processing system, the processing system including a plurality of computing resource units wherein at least two of the resource units are initially allocated to a first application, and wherein the processing system has insufficient resources to simultaneously run both of the first application and a second application at full capacity, the method including de-allocating fewer than all of the resource units allocated to the first application, then allocating at least one resource unit to the second application, and then de-allocating at least one resource unit from the first application.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: June 12, 2012
    Assignee: International Business Machines Corporation
    Inventors: Ea-Ee Jan, Benoit Emmanuel Maison
  • Patent number: 8199970
    Abstract: An arithmetic device (400) calculates a moving amount based on an image sensed before movement and an image sensed after movement. The arithmetic device (400) generates a difference image with minimum noise using the calculated moving amount. The arithmetic device (400) removes noise from the difference image by performing image processing of the difference image. The arithmetic device (400) determines based on the size of a binarized region in a binarized difference image whether an obstacle exists. This makes it possible to accurately calculate the moving amount and accurately determine whether an obstacle exists.
    Type: Grant
    Filed: June 6, 2007
    Date of Patent: June 12, 2012
    Assignee: NEC Corporation
    Inventor: Tatsuo Akiyama
  • Patent number: 8193838
    Abstract: An input circuit, includes a first buffer circuit, a second buffer circuit, a first differential amplification circuit that includes a first input coupled to a first external power source terminal, a second input coupled to an output of the first buffer circuit, and an output coupled to an input of the first buffer circuit, and a second differential amplification circuit that includes a first input coupled to a second external power source terminal, a second input coupled to an output of the second buffer circuit, and an output coupled to an input of the second buffer circuit.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yuji Nakajima
  • Patent number: 8193865
    Abstract: An output circuit includes an analog amplifier circuit including a differential amplifier stage configured to receive an input voltage, and first to nth output systems (n is a natural number more than 1); first to nth output nodes; an output pad; and first to nth electrostatic protection resistances. An ith output system (i is a natural number between 2 and n) of the first to nth output systems includes an ith PMOS transistor having a drain connected with the ith output node of the first to nth output nodes and a gate connected with a first output of the differential amplifier stage; and an ith NMOS transistor having a drain connected with the ith output node and a gate connected with a second output of the differential amplifier stage. The first to nth electrostatic protection resistances are respectively connected between the first to nth output nodes and the output pad.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kouichi Nishimura
  • Patent number: 8189529
    Abstract: A mobile communication system including a base station which divides a transmission frequency band into a plurality of frequency blocks, and assigns radio resources to each mobile station for each of the frequency blocks, the base station including: a frequency block assignment information creation portion that creates frequency block assignment information based on a downlink signal reception status and a downlink signal reception status degradation rate in each mobile station; and a radio resource assignment portion that assigns the radio resources to each frequency block based on the frequency block assignment information.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: May 29, 2012
    Assignee: NEC Corporation
    Inventor: Masato Shiokawa
  • Patent number: 8189545
    Abstract: There is provided a wireless LAN access point capable of confirming and changing the setting using the IP communication for a target wireless LAN access point positively even when the IP address of the wireless LAN access point is forgotten. The wireless LAN access point, upon receipt of a probe request, transmits a probe response while at the same time starting to transmit a beacon frame required to be periodically transmitted. The wireless LAN access point starts the DHCP server therein at the same time that the process of associating the wireless LAN station is started. The DHCP server operates only for the wireless interface of the wireless LAN access point and the wireless LAN station associated by use of the maintenance SSID. The wireless LAN access point, upon complete association of the wireless LAN station with the local access point, leases the IP address to the wireless LAN station from the DHCP server in the particular local access point.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: May 29, 2012
    Assignee: NEC Infrontia Corporation
    Inventors: Takeshi Irie, Hideki Kurokawa
  • Patent number: 8190856
    Abstract: A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access control lines, each access control line being connected to each PE of the first and second PEs to control data access timing between each PE and the network. Each PE can be self-controlled or common controlled, such as dual mode SIMD/MIMD architectures, reducing the wiring area requirement.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: May 29, 2012
    Assignee: NEC Corporation
    Inventors: Hanno Lieske, Shorin Kyo
  • Patent number: 8183957
    Abstract: There is provided a radio communication apparatus for transmitting transmission signals of the channel CH1 and the channel CH2, including a first antenna, a second antenna, a dual-band transmitting/receiving circuit having a first terminal for the channel CH1 and a second terminal for the channel CH2, a first branching circuit configured to receive a transmission signal from the first terminal or the second terminal, a second branching circuit configured to divide the transmission signal from the first branching circuit between the first antenna and the second antenna, and a transmission line configured to connect the first branching circuit and the second branching circuit.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasufumi Sasaki, Takuji Mochizuki
  • Patent number: 8185480
    Abstract: A method of optimizing a function of a parameter includes associating, with an objective function for initial value of parameters, an auxiliary function of parameters that could be optimized computationally more efficiently than an original objective function, obtaining parameters that are optimum for the auxiliary function, obtaining updated parameters by taking a weighted sum of the optimum of the auxiliary function and initial model parameters.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Dimitri Kanevsky, David Nahamoo, Daniel Povey, Bhuvana Ramabhadran