Patents Represented by Attorney McGinn Intellectual Property Law Group, PLLC
  • Patent number: 8117513
    Abstract: In a combinational portion, when there is one or more unspecified bits in pseudo external input lines and there is no unspecified bit in pseudo external output lines, an assigning operation is carried out. In the combinational portion, when there is one or more unspecified bits in the pseudo external output lines and there is no unspecified bit in the pseudo external input lines, first and second justifying operations are carried out, and a necessary logic value is determined for an unspecified bit of the test cube. In the combinational portion, when there are one more unspecified bits not only in the pseudo external input lines but also the pseudo external output lines, an assigning operation, a justifying operation or first and second assigning/justifying operations are performed upon a focused bit pair.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: February 14, 2012
    Assignee: LPTEX Corporation
    Inventors: Xiaoqing Wen, Seiji Kajihara
  • Patent number: 8112762
    Abstract: A blade server includes a management blade and managed blade. The management blade manages service data necessary for the service of an application. In the managed blade, the application is activated. The managed blade includes a service data list creation unit and service data list transmission unit. The service data list creation unit creates a service data list representing service data necessary for the service of the application. The service data list transmission unit transmits the service data list created by the service data list creation unit to the management blade. The management blade includes a service data transmission unit. The service data transmission unit transmits, to the managed blade, service data in the service data list transmitted from the service data list transmission unit before the service of the application starts. A service start method for a blade server is also disclosed.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: February 7, 2012
    Assignee: NEC Corporation
    Inventor: Takashi Shokawa
  • Patent number: 8110907
    Abstract: A semiconductor device includes a semiconductor chip, a first substrate, and a second substrate. The first substrate includes a plurality of wires and a plurality of first electrodes, each first electrode being connected with each wire. The second substrate includes the semiconductor chip that is mounted thereon, and a plurality of second electrodes with, each second electrode being connected with the each first electrode of the first substrate. The widths of the wires of the first substrate are different depending on the lengths of the wires. By changing the widths of the wires depending on their lengths, it is possible to reduce variation in stiffness of the electrodes and vicinities of electrodes, whereby variation in ultrasonic bonding strength can be reduced.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: February 7, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Masahiro Yamaguchi, Emi Sawayama, Hiroshi Oyama, Shigeharu Tsunoda, Yasuo Amano, Naoki Matsushima
  • Patent number: 8109636
    Abstract: The invention provides an illumination optical system that guides light emitted from light source device 1 to DMD 2, the illumination optical system including: light tunnel 20 that uniformizes luminance distribution of light emitted from light source device 1; relay optical system 40 that guides light having uniformized illumination distribution to DMD 2; and shield board 30 disposed on an optical path between light tunnel 20 and relay optical system 40. Shield board 30 is smaller than outlet end face 22 of light tunnel 20 and at the same time has an opening of a shape similar to the image formation area on DMD 2, and is movable in a plane containing the opening.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: February 7, 2012
    Assignee: NEC Display Solutions, Ltd.
    Inventor: Jun Ogawa
  • Patent number: 8105445
    Abstract: A method (and structure) of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: January 31, 2012
    Assignees: International Business Machines Corporation, Qimonda AG
    Inventors: Ulrich Karl Klostermann, Wolfgang Raberg, Philip Trouilloud
  • Patent number: 8106505
    Abstract: An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 31, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Thomas Brunschwiler, Bruno Michel
  • Patent number: 8107538
    Abstract: A moving image distribution system is capable of making phase adjustment of video data and audio data while preventing the cost of a display apparatus from increasing, by adjusting time information with a moving image distribution server. The moving image distribution server stores moving image data, reads the moving image data, changes information included therein as to decoding times or reproducing times of video data or audio data included in the moving image data based on a predetermined phase adjustment variable, and then distributes the moving image data. A reproducing apparatus receives the moving image data distributed from the moving image distribution server, decodes the moving image data according to the information included therein as to the decoding times and the reproducing times, and reproduces the moving image data.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: January 31, 2012
    Assignee: NEC Viewtechnology, Ltd.
    Inventors: Hisakazu Aoyanagi, Tomohiro Mihara
  • Patent number: 8107203
    Abstract: According to an embodiment of the present invention, an electrostatic discharge protection circuit used for a semiconductor device including a first power supply terminal, a second power supply terminal, and an input/output terminal, includes: a thyristor passing a surge current from the input/output terminal to the second power supply terminal; and a bipolar transistor passing a surge current from the first power supply terminal to the input/output terminal.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takayuki Nagai
  • Patent number: 8106681
    Abstract: In a method of programming a differential programming semiconductor device, first identification data corresponding to first program data is outputted from an ID register of a program circuit in the device to a host. The first program data is programmed in a plurality of interconnections. The first program data is read from a storage unit based on the first identification data. Write data is generated based on the first program data and a second program data, which is to be newly programmed in the plurality of interconnections. The write data is transferred from the host to the device. The write data is written in the plurality of interconnections by the program circuit so as to program the second program data in the plurality of interconnections.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: January 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Tadashi Fujita
  • Patent number: 8102011
    Abstract: There is provided a semiconductor device including a field effect transistor. The field effect transistor includes a p-type low concentration region formed over a surface of a substrate, an n-type drain-side diffusion region and an n-type source-side diffusion region formed over a surface of the p-type low concentration region, an element isolation insulating layer, and another element isolation insulating layer. A p-type high concentration region, which has an impurity concentration higher than the impurity concentration of the p-type low concentration region, is formed below the n-type source-side diffusion region in the p-type low concentration region over a range at least from one end, which is opposite to the other end facing to the channel region, of the source-side diffusion region to one end, which is facing to the channel region, of the second element isolation insulating layer, when seen in a plan view.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroki Fujii
  • Patent number: 8101939
    Abstract: A GaN single-crystal substrate has a substrate surface in which polarity inversion zones are included. The number density of the polarity inversion zones in the substrate surface is not more than 20 cm?2. A GaN single crystal production method includes introducing group III and V raw material gases on a substrate, and growing a GaN single crystal on the substrate. The growth temperature is within the range of not less than 1100° C. and not more than 1400° C., the group V to III raw material gas partial pressure ratio (V/III ratio) is within the range of not less than 0.4 and not more than 1, and the number density of polarity inversion zones in a surface of the substrate is not more than 20 cm?2.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: January 24, 2012
    Assignee: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Masatomo Shibata
  • Patent number: 8096705
    Abstract: A method of estimating temperature of a transient nature of a thermal system, including, without a temperature measurement being made available, determining a drive current and thermal parameters of the thermal system.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Sri M. Sri-Jayantha, Hien P. Dang, Arun Sharma
  • Patent number: 8098137
    Abstract: A media passport system including a radio frequency identification (RFID) transponder attached to a removable medium a plurality of RFID readers installed in rooms, wherein each RFID reader has a unique identification (ID), and a security server connected to the plurality of RFID readers via a network. The security server hosts a zone-table including a unique ID information of the removable medium, and a zone information determined as a subset of the unique IDs of the plurality of RFID readers. Based on this the security server sends an alarm when a removable medium is transported inside or outside a zone.
    Type: Grant
    Filed: March 29, 2008
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nils Haustein, Craig A. Klein, Frank Krick, Daniel J. Winarski
  • Patent number: 8094109
    Abstract: A multilevel voltage generating circuit includes first and second input nodes provided on a first resistance element and supplied with first and second reference voltages. A current substantially flows in a first specific area for a line between the first and second input nodes based on a difference between the first and second reference voltages. A first group of output nodes are provided for the first resistance element to output a portion of a plurality of level voltages. A first one of the first group of output nodes for one of the plurality of level voltages which is closest to the first reference voltage is provided outside the first specific area. The first output node, the first input node, and the second input node, are arranged on a line on the first resistance element in this order.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Junichirou Ishii, Hiroshi Tsuchi
  • Patent number: 8093927
    Abstract: A semiconductor device, having a test circuit of a multivalued logic circuit without newly provision of an output terminal for a test signal, and with no increase in transmission delay in an output signal, includes an n-valued input terminal, and comparators that operate at different threshold voltages in response to input signals which have been input to the n-valued input terminal, respectively, and also includes an impedance control circuit that is connected to the n-valued input terminal and outputs of the comparators, respectively, and changes a combine resistance value in response to the output signals of the comparators to change a current flowing in the n-valued input terminal.
    Type: Grant
    Filed: December 16, 2009
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshitomo Numaguchi, Munehisa Okita
  • Patent number: 8094113
    Abstract: A liquid crystal display apparatus includes a plurality of data lines; a plurality of scan lines which intersect the plurality of data lines; pixels arranged at intersections of the plurality of data lines and the plurality of scanning lines; and a data line driving circuit configured to drive the plurality of data lines, and comprising a first data line driving section and a second data line driving section. 4×n (n: an optional natural number) frames are set as one cycle, and each of the plurality of data lines is circularly driven by one of the first data line driving section and the second data line driving section during one cycle.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Junya Yokota, Yoshiharu Hashimoto
  • Patent number: 8094700
    Abstract: A communication device includes a transmitter and a receiver. The transmitter includes a transmission-side code generator and a first spread unit for example. The receiver includes a reception-side code generator and a first inverse spread unit for example. The transmission-side code generator generates a spread code comprised of a spread code scheduled according to a difference of a transmission cycle of an input signal. The first spread unit performs spread spectrum processing on the input signal by the spread code. The reception-side code generator generates a spread code in use for performing inverse spread spectrum processing on a receiving signal. The first inverse spread unit performs inverse spread spectrum processing on the receiving signal by the spread signal generated at the code generator.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: January 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Osamu Okazaki
  • Patent number: 8085234
    Abstract: A capacitive load driving circuit includes a gate driver, and a source driver. The gate driver drives a plurality of capacitive loads arranged in a matrix form in a row direction. The source driver drives the plurality of capacitive loads in a column direction. The source driver includes a plurality of output circuits configured to be arranged in a row direction. Each of the plurality of output circuits changes a slew rate based on a column position of a capacitive load of the plurality of capacitive loads driven by the gate driver.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kouichi Nishimura, Takashi Nose
  • Patent number: 8085078
    Abstract: A level shift circuit includes a first resistor with one end connected to GND, a first transistor with a drain and a gate connected to the other end of the first resistor, and a source connected to a first power supply, a second transistor with a source connected to the first power supply, and a gate connected to the drain and the gate of the first transistor, a second resistor with one end connected to a drain of the second transistor, a third transistor with a source connected to the other end of the second resistor, and a gate connected to an input terminal, a first current source connected between a second power supply and a drain of the third transistor; and a fourth transistor connected between an output terminal and the first power supply with a gate connected to the drain of the second transistor.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuri Honda
  • Patent number: 8080861
    Abstract: A semiconductor device includes an electric fuse and first and second large area wirings for applying a voltage to the electric fuse. The electric fuse includes a fuse unit which includes an upper-layer fuse wiring, a lower-layer fuse wiring, and a via connecting the upper-layer fuse wiring and the lower-layer fuse wiring, an upper-layer lead-out wiring which connects the upper-layer fuse wiring and the first large area wiring and has a bent pattern, and a lower-layer lead-out wiring which connects the lower-layer fuse wiring and the second large area wiring and has a bent pattern.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: December 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Tsuda, Yoshitaka Kubota, Hiromichi Takaoka