Abstract: An image transmitting method is disclosed for reducing the load on a CPU of an image transmission apparatus. An image change monitoring unit provided in the image transmission apparatus monitors the latest image used to generate image data transmitted to an image reception apparatus via a network, and a subsequent image to determine whether or not the latest image has changed. An image capture unit captures the image after the image has changed to acquire the image when the image change monitoring unit determines that the latest image has changed.

Abstract: A data line drive circuit includes a plurality of output circuits and a plurality of switch portions. The plurality of output circuits outputs voltages corresponding to grayscale voltages with respect to display data. The plurality of switch portions becomes an ON-state in response to a line output signal and connects the plurality of output circuits and a plurality of data lines, respectively. ON-resistance values of at least part of the plurality of switch portions vary in the ON-state.

Abstract: A magnetic material antenna using a ferrite sintered body comprising one or more conductors disposed at least on a surface or in internal portion of the ferrite sintered body, wherein the ferrite sintered body is a sintered body of Y-type ferrite containing BaO, CoO, and Fe2O3 as main components and wherein the ferrite sintered body contains Cu and, in a cross section for the sintered body, an area rate of a cubic Co-rich phase, which has a ration of an amount of Co being higher than a Y-type ferrite phase being a mother phase, is 1% or less.

Abstract: The invention provides a semiconductor device including a plurality of stacked semiconductor chips, which offers a higher degree of freedom in selecting a chip size of the semiconductor chip and arranging the routing, and increase of the reliability and speed in signal transmission between the semiconductor chips. The semiconductor device includes a lower semiconductor chip, an upper semiconductor chip and a silicon spacer formed between the lower semiconductor chip and the upper semiconductor chip and including a projecting portion projecting farther outward than an outer periphery of the upper semiconductor chip, and the silicon spacer includes through electrodes and reroutings.

Abstract: To improve the precision of temperature compensation in an infrared sensor and obtain a sharp image, a correction is applied to a variation in output voltage (referred to as “background infrared radiation absorption intensity distribution” below) due to intensity distribution of background infrared radiation, which is light other than the incident infrared radiation on the infrared sensor, and the temperature characteristic of each individual bolometer constituting the infrared sensor. That is, the temperature of the infrared sensor is measured as a first temperature, a correction value for the output voltage of each bolometer is found by referring to a table, which indicates the background infrared radiation absorption intensity distribution versus the temperature of the infrared sensor, as well as the first temperature, and the variation in output voltage is corrected.

Abstract: A system for imprint lithography, which includes a substrate, a patterned mask, an imprint applying unit that imprints, via the patterned mask, a pattern into a resist layer on the substrate, and an overlay device that overlays a cladding layer over the substrate.

Abstract: A hierarchical design apparatus 1 for a semiconductor integrated circuit includes a hierarchical block placing unit 1-02 which places sets of hierarchical blocks onto a chip; a hierarchical block terminal placing unit 1-03 which places terminals of the hierarchical blocks so that for sets of hierarchical blocks having the same function, the hierarchical blocks coincide with each other in a coordinate of the corresponding terminal; an intra-hierarchical block layout unit 1-06 which executes the individual types of intra-hierarchical-block layout designs, meanwhile executes only a single type of intra-hierarchical-block layout design for the sets of hierarchical blocks having the same function; and a chip layout finishing unit 1-07 which replicates thus-obtained layout patterns, and thereby completing a layout design over the entire chip.

Abstract: A system and method for managing computer operations according to stored user preferences is disclosed. The system includes a calendar module for scheduling an event and centrally storing the user preferences regarding the computer operations during the event, and a controller module for retrieving the user preferences centrally stored in the calendar module and centrally controlling the computer operations according to the user preferences during the event.

Abstract: A method (and system) for causal modeling includes modeling a data set. The modeling includes estimating a reverse Bayesian forest for the data set and detecting outliers in a separate data set. Detecting the outliers includes applying the reverse Bayesian forest to the separate data set to obtain a probability value assigned to data points in the separate data set and identifying outliers in the separate data set by evaluating the probability value given by the reverse Bayesian forest.

Abstract: An execution management method includes providing an execution plan, balancing an execution load across a plurality of servers, automatically interpreting the execution plan, and re-driving a failed test to another of the plurality of servers if the test case fails on an originally selected available server. The execution plan includes a plurality of test cases and criteria corresponding to the test cases. More than one of the plurality of test cases may be run on each of the plurality of servers at a same time in parallel. Each of the plurality of servers is run independently.

Abstract: A method (and apparatus) of imprint lithography, includes imprinting, via a patterned mask, a pattern into a resist layer on a substrate, and overlaying a cladding layer over the imprinted resist layer. A portion of the cladding layer is used as a hard mask for a subsequent processing.

Abstract: A thermoelectric transducer is provided, where a decrease in conversion efficiency due to uneven characteristics of semiconductors is resolved and a decrease in adhesion strength between each element unit and an electrode due to a heat expansion coefficient between the respective thermoelectric transducers. In addition, an improvement of electro thermal conversion efficiency is intended by modifying the structure of the single device. Single element unit (13), which are made off semiconductor of the same type constructed of sintered body cells each containing oxide of a metal element, an oxide of a rare-earth element, and manganese are arranged on a board (5, 12) of a thermoelectric transducer (10). Film-shaped thin-film electrodes are arranged on cooling and heating surfaces so to be integral with the sintered body cell. On these sides, lead wires (16) are connected to each other in series.

Abstract: A method (and system) of discovering a significant subset in a collection of documents, includes identifying a set of documents from a plurality of documents based on a likelihood that documents in the set of documents carries an instance of information that is characteristic to the documents in the set of documents.

Abstract: A digital-analog conversion circuit includes a correction unit that adds a correction bit to a lower-order bit of externally input first digital input data and outputs second digital input data, and a conversion unit that receives the second digital input data and outputs an analog value, and the correction unit generates the second digital input data by manipulating data of a lower-order bit of the second digital input data around a point at which an error between the analog value and an expected value set for the first digital input data becomes larger than a preset value.

Abstract: A frequency divider section generates a frequency-divided clock RSELO by dividing the frequency of an internal clock LCLK, which lags behind an external clock in phase, and generates a delayed frequency-divided clock RSELI by delaying the frequency-divided clock RSELO. A signal input from the outside in synchronization with an internal clock PCLK which lags behind the external clock in phase is held in a latch circuit in synchronization with the delayed frequency-divided clock RSELI. Then, an output signal of the latch circuit is read into a latch circuit in synchronization with the frequency-divided clock RSELO and is output as a signal which is synchronized with the internal clock LCLK. In addition, a frequency divider section includes a variable divider which divides the frequency of the internal clock LCLK by a predetermined divide ratio which can be changed.

Abstract: A memory control circuit includes a conversion circuit performing a conversion processing for parallel readout bit data formed from individual bits read out from memory cells of a nonvolatile memory, by setting the individual bit that is once again read out from the memory cell, which is previously determined to be successfully storing an expectation value, to a corresponding expectation value expected to be stored in the memory cell, and a determination circuit determining a result of a write processing to write parallel expectation value data to the nonvolatile memory, based on the parallel readout bit data converted by the conversion circuit and the parallel expectation value data.

Abstract: A packing material fitting structure that prevents the packing material from easily dropping out and facilitates mounting and fixing of the packing material in a packing material fitting place in a part such as a casing or a cover of an engine or a pump with sealing ability. The fitting structure is provided with a packing material having an annular main body portion and a plurality of projections each having a main protruding portion formed to protrude from the annular main body portion and an auxiliary protruding portion formed integrally in the vicinity of the main protruding portion, the projections being formed with an appropriate spacing in the longitudinal direction of the main annular main body portion. The fitting structure is also provided with a casing having formed therein an annular fitting groove for inserting the annular main body portion of the packing material.

Abstract: A method of manufacturing a semiconductor device includes preparing two package substrates, electrically coupling a semiconductor wafer to a measuring apparatus, inspecting the wafer, dicing the semiconductor wafer into semiconductor elements and packaging the semiconductor element over the prepared package substrates.

Abstract: An electrostatic discharge protection device includes a first bipolar transistor having a collector terminal connected with a first power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with a second power supply terminal, a second bipolar transistor having a collector terminal connected with the second power supply terminal, an emitter terminal connected with the input/output terminal, and a base terminal connected with the first power supply terminal, one of the first and second bipolar transistors ensuring a continuity between the collector terminal and emitter terminal under such conditions that a potential difference between the first or second power supply terminal and the input/output terminal is lower than a breakdown voltage at a PN junction between the emitter terminal and the base terminal of the other bipolar transistor.

Abstract: In a combinational portion, when there is one or more unspecified bits in pseudo external input lines and there is no unspecified bit in pseudo external output lines, an assigning operation is carried out. In the combinational portion, when there is one or more unspecified bits in the pseudo external output lines and there is no unspecified bit in the pseudo external input lines, first and second justifying operations are carried out, and a necessary logic value is determined for an unspecified bit of the test cube. In the combinational portion, when there are one more unspecified bits not only in the pseudo external input lines but also the pseudo external output lines, an assigning operation, a justifying operation or first and second assigning/justifying operations are performed upon a focused bit pair.