Abstract: A weight piece (14) containing 15 wt. % or greater of iron and tungsten, and having a specific gravity of 9 or larger, larger than a material of a head body (10) made of steel or pure iron, is joined to the head body (10) by welding.

Abstract: There is provided a radio communication apparatus for transmitting transmission signals of the channel CH1 and the channel CH2, including a first antenna, a second antenna, a dual-band transmitting/receiving circuit having a first terminal for the channel CH1 and a second terminal for the channel CH2, a first branching circuit configured to receive a transmission signal from the first terminal or the second terminal, a second branching circuit configured to divide the transmission signal from the first branching circuit between the first antenna and the second antenna, and a transmission line configured to connect the first branching circuit and the second branching circuit.

Abstract: A method of optimizing a function of a parameter includes associating, with an objective function for initial value of parameters, an auxiliary function of parameters that could be optimized computationally more efficiently than an original objective function, obtaining parameters that are optimum for the auxiliary function, obtaining updated parameters by taking a weighted sum of the optimum of the auxiliary function and initial model parameters.

Abstract: A biometric sensor device, a portable electronic device including an actuatable biometric input device, and method of biometric authentication that includes an input device that generates a signal or completes a circuit when actuated, and a biometric reader that reads a biometric of a user when the user actuates the input device to generate the signal or complete the circuit. An authentication section authenticates the biometric read on the biometric reader to generate one of a data access allowance function based on authentication of the biometric input to the actuatable biometric input device and a data access prevention function based on non-authentication of the biometric input to the actuatable biometric input device. The data access allowance function permits data to be accessed at the data access interface, and the data access prevention function prevents reading and/or access to data anywhere on the data storage and access device.

Abstract: An electrical fuse including a polysilicon layer; a silicide layer formed over the polysilicon layer; and a first metal contact and a second metal contact arranged over the silicide layer, while being spaced from each other, the electrical fuse being configured so that the silicide layer, after disconnection, is excluded from a region right under the second metal contact, and from a region between the second metal contact and the first metal contact is provided.

Abstract: A data processing method comprises receiving an electronically parseable document, scanning the document according to at least one predefined rule to determine if the document is suspicious, and, if the document is determined not to be suspicious, parsing the document with a first parser, and, if the document is determined to be suspicious, parsing the document with a second parser.

Abstract: A tilt steering apparatus comprises a tilt adjusting mechanism in which a tilt lock release is established only when an oscillation-free end of an operating arm portion of a tilt operating lever is positioned toward a steering wheel side. Even when the tilt operating lever is oscillated to the steering wheel side, the tilt operating lever is prevented from returning under its own weight, thereby preventing it from being difficult to operate. The tilt steering apparatus is configured from an oscillation latch portion formed on the circumference of an oscillation center portion of an oscillation base portion of the tilt operating lever to move reciprocally in the circumferential direction, a hook portion formed in the movable bracket, and a spring that extends between the oscillation latch portion and the hook portion elastically urged in the direction of contraction. The centerline of the spring is able to pass through the oscillation center portion of the tilt operating lever as appropriate.

Abstract: A device control is disclosed for controlling a device with a high-priority signal without interference by a low-priority signal. Panel keys, which serve as a high-priority signal receiver unit, receives a high-priority signal. A panel key signal processing unit, which is a high-priority signal processing unit, processes the signal received by the panel keys. A remote control signal receiver unit, which is a low-priority signal receiver unit, receives a low-priority signal. A remote control signal processing unit, which is a low-priority signal processing unit, processes the signal received by the remote control signal receiver unit. A remote control signal reception control unit, which is a low-priority signal processing control unit, disables the processing in the remote control signal processing unit when the panel key signal processing unit is performing the processing.

Abstract: A card gaming machine including: an extraction unit for extracting at least a card from among a plurality of the cards with a predetermined kinds of symbols drawn thereon; a display unit for displaying an image of the cards extracted by the extraction unit and dealt to a player as the cards in player's hand; and a control unit for producing image effect on the display unit in response to the deal situation of the cards in player's hand displayed as an image by the display unit.

Abstract: A hub unit is equipped with an inner member having an inner ring raceway formed on its outer peripheral face, an outer member having an outer ring raceway formed on its inner peripheral face, and a plurality of rolling elements provided between the inner ring raceway and the outer ring raceway. At least one of the inner ring raceway and the outer ring raceway has a rolling contact zone on which an induction-hardened layer is formed. The hardened layer has a depth of about 1.5 to 1.9 mm at a distance of 1 mm inward from each end of the hardened layer.

Abstract: A leadframe has a die pad, first marks, and second marks, and the die pad allows thereon mounting of a first semiconductor chip. The first marks indicate a mounting region for the first semiconductor chip, the second marks indicate a mounting region for the second semiconductor chip, and the first marks and the second marks are different from each other in at least either one of size and geometry.

Abstract: A semiconductor memory apparatus includes an SRAM circuit having first SRAM cells that store data and second SRAM cells that amplify a potential difference of the data and store the potential difference, a word line driver circuit that outputs a first control signal for selecting one of the first SRAM cells to be read/written the data and a second control signal for selecting one of the second SRAM cells to be read/written the potential difference, a sense amplifier circuit that amplifies a potential difference of a read signal output from a bit line pair of the second SRAM cell selected according to the second control signal, and a write driver circuit that outputs a write signal to the bit line pair of the second SRAM cell selected according to the second control signal, and the write signal has a potential difference between bit lines larger than the read signal.

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: Provided is a clock gating circuit which receives a first clock signal and controls an output of a second clock signal corresponding to the first clock signal in response to a control signal. The clock gating circuit includes: a first latch that latches a signal value of the control signal in synchronization with the first clock signal; an AND that receives the first clock signal and controls an output of the second clock signal in response to an output signal of the first latch; and a second latch that latches a signal value of the output signal of the first latch in synchronization with the first clock signal, and outputs a latched value. This enables execution of a scan test with a simple circuit configuration.

Abstract: A method of implementing a complete SAP system landscape on IBM System i is provided. This method involves preselecting at least one value-added reseller (VAR) for participation in implementing the complete SAP system landscape on IBM System i. The VAR then selects values for flexible parameters according to needs of a customer. The flexible parameters include languages for i5/OS and SAP, an amount of SAP ERC Central Component (ECC) systems ranging from one to three, an inclusion of a SAP Solution Manager, a client landscape, a configuration of SAP systems, and a level of software stack. The level of software stack includes a layer of the SAP systems, a layer implementing country-specific configuration, a layer implementing industry-specific configuration, and a layer of VAR added value. Media is created and implemented with the specified content at a factory using standard SAP procedures. A full backup of the SAP systems is then created using standard i5/OS operating system imaging.

Abstract: The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction from an instruction fetched from the memory unit by the CPU. The mode control section changes an operation mode of the memory unit according to a detection result by the branch detection section.

Abstract: In a computer system supporting memory compression and wherein data is stored on a disk in a different compressed format, and wherein an IOA (input/output adaptor)/IOP (input/output processor) selectively reads from and writes to a main memory through a direct memory access (DMA) operation, a method for transmitting compressed data from the IOA/IOP to the main memory includes reserving a set of free memory sectors to contain the data in said main memory, sending to the IOA/IOP addresses of said memory sectors, copying the data from the IOA/IOP to said memory sectors using said DMA operation, constructing at the IOA/IOP compressed memory directory information defining how and where the data is stored in memory, sending the memory directory information to a memory controller, and storing the memory directory information in the compressed memory directory structure.

Abstract: In current driving circuit a desired value of a driving current is promptly written in a load of each pixel despite load variations that may occur in each pixel. A constant current source circuit delivers a driving current Idata to a load. An output voltage difference amplifier circuit detects a voltage change produced at a load driving end within a preset time period, and delivers a current or a voltage corresponding to the voltage change during a time period different from the preset time period. The output voltage difference amplifier circuit temporally repeats detection of the voltage change and delivery of the current or the voltage to the load.

Abstract: A delay-type phase adjusting circuit including a first variable delay circuit for receiving a reference clock signal and adding a delay to the reference clock signal, for output a phase comparator for receiving an output of the first variable delay circuit and the reference clock signal and detecting a phase difference therebetween a control circuit for generating a control signal for variably controlling a delay value of the first variable delay circuit based on a result of phase comparison by said phase comparator a second variable delay circuit for receiving an input signal and adding a delay to the input signal, for output a computation circuit for receiving a predetermined value and the control signal and variably controlling a delay value of the second variable delay circuit.

Abstract: An image transmitting method is disclosed for reducing the load on a CPU of an image transmission apparatus. An image change monitoring unit provided in the image transmission apparatus monitors the latest image used to generate image data transmitted to an image reception apparatus via a network, and a subsequent image to determine whether or not the latest image has changed. An image capture unit captures the image after the image has changed to acquire the image when the image change monitoring unit determines that the latest image has changed.