Patents Represented by Attorney McGinn Intellectual Property Law Group, PLLC
  • Patent number: 7886248
    Abstract: The present invention is a method that a redundant via is never added afterwards for a signal wiring or a clock wiring, but layout is performed using a multi-cut via from the beginning, which is used for laying out a semiconductor integrated circuit by a step (S32) of searching a wiring route that layout is possible using a multi-cut via regarding a net in a net list, a step (S33) of laying out a wiring corresponding to the net on the wiring route with using the multi-cut via, and a step (S70) of creating layout data of the semiconductor integrated circuit by repeating the steps S32 and S33.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: February 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Katsuhisa Hirota
  • Patent number: 7884421
    Abstract: In a high voltage MOS transistor, in a portion immediately below the gate electrode, peaks of concentration distribution in depth direction of a first conductivity type impurity and a second conductivity type impurity in the drain offset region are in the same depth, the second conductivity type impurity being higher concentrated than the first conductivity type impurity.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: February 8, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Yanagigawa
  • Patent number: 7884381
    Abstract: A light emitting device includes a semiconductor multilayer structure having a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, and an active layer. A reflecting layer is provided at a side of one surface of the semiconductor multilayer structure and reflects a light emitted from the active layer. A supporting substrate of Si or Ge is provided at an opposite side of the reflecting layer with respect to the side of the semiconductor multilayer structure and supports the semiconductor multilayer structure via a metal bonding layer. A back surface electrode is provided at an opposite side of the supporting substrate with respect to a side of the metal bonding layer and includes Au alloyed with the support substrate. A hardness of the back surface electrode is higher than a hardness of the Au.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: February 8, 2011
    Assignee: Hitachi Cable, Ltd.
    Inventors: Masahiro Arai, Kazuyuki Iizuka
  • Patent number: 7880721
    Abstract: An ultrasonic receiver receives an ultrasonic signal having a period in which an amplitude thereof progressively increases as time elapses. A pattern matching unit determines whether a comparative pattern, which is generated as a result of comparison between the respective maximum amplitude values of a plurality of successive waves of said wave signal and a threshold value set by a threshold setting unit, matches a reference pattern or not during the period of the ultrasonic signal. The pattern matching unit determines that the ultrasonic receiver has successfully received the ultrasonic signal if the comparative pattern matches the reference pattern.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: February 1, 2011
    Assignee: NEC Viewtechnology, Ltd.
    Inventors: Kenji Suzuki, Hiroyuki Kobayashi, Syuuji Murayama, Kenji Inamoto
  • Patent number: 7869522
    Abstract: An embodiment of the present invention provides a video signal multiplexing apparatus including a separator separating picture information and additional information from a received video signal, a controller adjusting, if the picture information is out of sync with the additional information, a data amount of the additional information based on a data amount of the picture information in such a manner that the picture information is in sync with the additional information, and a multiplexer multiplexing the encoded data and the additional information the data amount of which has been adjusted.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: January 11, 2011
    Assignee: NEC Electronics Corporation
    Inventors: Tomoyuki Okuyama, Kenji Tanaka
  • Patent number: 7864608
    Abstract: A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the DRAM cell. A power supply circuit supplies the power supply voltages to the sense amplifier. A sense amplifier dummy circuit provides a replica of a state of the sense amplifier immediately after the activation of the sense amplifier; and a power supply control circuit controls the power supply circuit based on the replica such that the power supply voltages are varied with time.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Takahashi
  • Patent number: 7865789
    Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Serafino Bueti, Adam Courchesne, Kenneth J. Goodnow, Gregory J. Mann, Jason M. Norman, Stanley B. Stanski, Scott T. Vento
  • Patent number: 7860153
    Abstract: A method, and a mobile terminal incorporating the same, of carrying out a reception decision uses a signal received from a base station in the mobile terminal. The mobile terminal includes a communication parameter calculating unit for calculating a communication parameter that is used for estimating a state of a communication environment based on a reception signal transmitted from a base station, a decision parameter setting unit for calculating a decision parameter based on a result of estimation for the state of the communication environment generated by using the communication parameter calculated by the communication parameter calculation unit, and a reception decision unit for carrying out a reception decision of the reception signal based on the decision parameter set by the decision parameter setting unit.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: December 28, 2010
    Assignee: NEC Corporation
    Inventor: Kazunori Sato
  • Patent number: 7860148
    Abstract: A receiving circuit which receives information using a multi-carrier signal comprises a phase rotation amount calculator which calculates a phase rotation amount of a multi-carrier signal included in a first frequency band according to a pilot-sub carrier included in the first frequency band, a converter which calculates a phase rotation amount of a multi-carrier signal included in a second frequency band according to the phase rotation amount of the multi carrier signal included in the first frequency band.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: December 28, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takahiro Sato
  • Patent number: 7859097
    Abstract: A semiconductor device including a semiconductor chip having external connecting terminals formed on one side is restrained to cause chipping in ridge line portion of semiconductor chip. A cover layer 103 is formed on the other side of the semiconductor chip 102. At least a part of an end portion 106 of the cover layer is outside of the ridge line portion 107 of the semiconductor chip.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Kousaku Uoya
  • Patent number: 7859509
    Abstract: In a semiconductor integrated circuit device, a shift register includes a plurality of cascaded flip-flops adapted to generate shift pulse signals in response to a start signal. A logic circuit receives a pulse signal at its input end and supplies the pulse signal from its plurality of output ends to the flip-flops. The pulse signal at each of the plurality of output ends is allowed and prohibited by a corresponding one of the shift pulse signals.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: December 28, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Toshiaki Ueda
  • Patent number: 7854157
    Abstract: The method, in which base material ingot 1 is heated and softened in an electric furnace 3, drawn with a pair of pinch roller 6 and 6, and elongated to make base material rod 7 having a smaller diameter than the ingot, features: forming either a roller groove 11 having a curvature radius which is larger than the outer diameter of the base material rod 7 or a V-shaped roller groove 11 having the cross section consisting of straight lines on the surface of the pinch roller 6 made of metal; nipping with the facing roller grooves 11 and 11 respectively formed on the surfaces of a pair of said pinch rollers 6 and 6; and drawing said base material rod.
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: December 21, 2010
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Soichiro Kemmochi, Waichi Yamamura, Takaaki Nacao, Mitsukuni Sakashita
  • Patent number: 7855981
    Abstract: A node that configures a spanning tree over a network to which a plurality of nodes are connected generates a tree after a cost change using another LAN while continuing to operate the tree that existed before the change, and switches the tree that is used for forwarding after the new tree has been stable.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: December 21, 2010
    Assignee: NEC Corporation
    Inventors: Nobuyuki Enomoto, Masaki Umayabashi, Youichi Hidaka, Atsushi Iwata, Makoto Shibutani
  • Patent number: 7854824
    Abstract: A method of manufacturing a semiconductor device includes measuring the reflectance at the surface of a semiconductor substrate provided with concave portions and deciding a deposition parameter that represents a deposition condition corresponding to the measured reflectance. Then, a metal film is formed on the semiconductor substrate under a condition corresponding to the deposition parameter.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: December 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventor: Akira Furuya
  • Patent number: 7849295
    Abstract: A data processing apparatus includes an operation processing unit and a data feature determining circuit. The operation processing unit is configured to sequentially perform preset operation processing on operation data in units of sub blocks to output an operation resultant data. Each of the operation data is divided into blocks, each of which comprises the sub blocks. The data feature determining circuit is configured to control the operation processing unit in units of blocks based on feature data respectively added to the blocks to indicate features of the blocks.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: December 7, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Sugimoto
  • Patent number: 7842893
    Abstract: The present invention aims to provide an electronic pen that is able to prevent the reflection of an ultrasonic wave. An electronic pen according to the present invention has: a housing having a longitudinal axis and a write side tip along the longitudinal axis; at least an ultrasonic wave transmitter, the ultrasonic wave transmitter being arranged near the write side tip of the housing; and a controller for detecting a sensor orientation and for controlling transmission of the ultrasonic wave. The sensor orientation is an index that shows a rotational orientation of the housing about the longitudinal axis, the rotational orientation being directed at an ultrasonic wave sensor for receiving the ultrasonic wave that is transmitted from the ultrasonic wave transmitter. The controller selectively activates a part of the ultrasonic wave transmitter such that the ultrasonic wave is transmitted from the orientation which is directed to the sensor orientation.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: November 30, 2010
    Assignee: NEC Viewtechnology, Ltd.
    Inventor: Shu Tomiya
  • Patent number: 7844210
    Abstract: According to an aspect of the present invention, there is provided a fixing apparatus including: a heat roller that includes: a heat source that generates heat to be supplied on a toner image formed on a recording medium; a cylindrical core; a rubber layer that is formed on the cylindrical core and includes a thermal-conductivity-enhanced rubber, the rubber layer having a thickness of Tg that satisfies 200 ?m?Tg?600 ?m and having a rubber hardness defined by JIS-A hardness of Hg that satisfies 40 degrees?Hg?80 degrees; and a fluororesin layer that is formed on the rubber layer, the fluororesin layer having a thickness of Tj that satisfies 80 ?m?Tj?300 ?m and 2 Tj?Tg?10 Tj; and a pressure roller that presses the recording medium against the heat roller.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: November 30, 2010
    Assignee: Ricoh Company, Ltd.
    Inventors: Sho Sawahata, Yuji Ohmura, Yoshikuni Sasaki
  • Patent number: 7839205
    Abstract: A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 23, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Atsunori Hirobe
  • Patent number: 7837394
    Abstract: A cage includes cage pockets for retaining rollers at plural positions along a circumferential direction of an annular plate. A projection extending in thickness direction of the cage is formed at a central part in the circumferential direction on an inner face of the cage pocket to pivotally support the roller. The projection is provided with a chamfered portion (non-contact portion) formed by chamfering an edge in the thickness direction, and a flat portion (contact portion) that is brought into contact with an opposing central portion in the thickness direction on a roller end face of the roller seated in o the cage pocket. The flat portion has a flat length almost equivalent to a displaceable distance of the cage in the thickness direction thereof.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: November 23, 2010
    Assignee: JTEKT Corporation
    Inventor: Wataru Takamizawa
  • Patent number: 7834770
    Abstract: A body weight threshold determination unit determines that the body weight of a user on a bed is at a body weight threshold or higher, and a center-of-gravity position area determination unit determines that the center-of-gravity position thereof has moved to an abnormal position (monitored area). In such a case, the bed user is detected to be in an abnormal position when a body weight center-of-gravity position monitoring unit detects that such a state has continued for a prescribed length of time or longer. When a back-raising operation has been carried out, a movable bedboard determination unit inputs the movable bedboard information, and a monitored area adjustment unit adjusts the monitored area. The monitored area is thereby constantly set to a suitable area in accordance with the state of the movable bedboard.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: November 16, 2010
    Assignee: Paramount Bed Co., Ltd.
    Inventor: Hiroki Kazuno