Patents Represented by Attorney McGinn Intellectual Property Law Group, PLLC
  • Patent number: 7995172
    Abstract: An electrically-floating light shielding film is formed on a glass substrate, and a signal line is formed above the light shielding film via a gate insulating film. The light shielding film is formed along the signal line, and has a width larger than that of the signal line. On an interlayer insulating film that covers the signal line, transparent electrodes of neighboring pixels are formed, and a reflective electrode extending from the transparent electrode has a frame portion disposed along the signal line. The reflective electrode is formed the interlayer insulating film. The light shielding film does not overlap the transparent electrode in a plan-view perspective and overlaps the reflective portion in a plan-view perspective. The signal line does not overlap the reflective electrode in a plan-view perspective. Hence, a semitransparent liquid crystal display device that suppresses vertical crosstalk and as well maintains a high aperture ratio is obtained.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: August 9, 2011
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Toshiya Ishii
  • Patent number: 7994614
    Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: August 9, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kouji Tanaka, Seiya Isozaki
  • Patent number: 7985686
    Abstract: A floating gate for a field effect transistor (and method for forming the same and method of forming a uniform nanoparticle array), includes a plurality of discrete nanoparticles in which at least one of a size, spacing, and density of the nanoparticles is one of templated and defined by a self-assembled material.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Kathryn Wilder Guarini
  • Patent number: 7986131
    Abstract: A booster power supply circuit includes a booster boosting an input voltage to output an boosted voltage for applying said boosted voltage to a first smoothing capacitor and a controller controlling a transfer destination and an amount of transfer of a charge in the first smoothing capacitor at a transition from an operation mode to a standby mode.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: July 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Sugiyama, Kiyoshi Miyazaki, Takashi Tahata
  • Patent number: 7986121
    Abstract: An inverter apparatus is for correcting deviations among current detectors of a three-phase motor. The inverter apparatus includes bidirectional switching elements that have on and off states in the cases in which there are 1 and 0 mean on- and off-states. The states are alternately repeated by controlling the switches, and measurement for correcting the deviations among the current detectors are obtained in the state Currents have the same amplitude flow on a U phase and a V phase. In the state of normal use, the inverter apparatus is operated by correcting detected current values based on the measurement data.
    Type: Grant
    Filed: April 22, 2008
    Date of Patent: July 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoichi Hayashi, Tetsuya Fukumoto
  • Patent number: 7987398
    Abstract: Disclosed is a reconfigurable device including at least a bus that mutually connects functional blocks, a configuration information memory disposed corresponding to each of the functional blocks, an error detection circuit that detects an error in the configuration information memory, and a buffer which is on-off controlled based on information stored in the configuration information memory and each of which controls connection between each of the functional blocks and each bus. When an error in the configuration information memory is detected by the error detection circuit, the buffer with an output thereof connected to the bus is set to an off-state, based on a result of error detection.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: July 26, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshirou Kitaoka, Taro Fujii
  • Patent number: 7986543
    Abstract: A method of electronic computing, and more specifically, a method of design of cache hierarchies in 3-dimensional chips, and a cache hierarchy resulting therefrom, including a physical arrangement of bits in cache hierarchies implemented in 3 dimensions such that the planar wiring required in the busses connecting the levels of the hierarchy is minimized. In this way, the data paths between the levels are primarily the vias themselves, which leads to very short, hence fast and low power busses.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventor: Philip George Emma
  • Patent number: 7983468
    Abstract: A method (and system) for extracting information from a document, includes segregating a set of documents from a plurality of documents based on a likelihood that at least one document in the set of documents carries an instance of a preset information.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 19, 2011
    Assignees: JP Morgan Chase Bank, International Business Machines Corporation
    Inventors: Tayo Ibikunle, Ehud Karnin, William A. Liberis, Tomasz J. Nowicki, Michael J. Reilly, Howard E. Sachar, Charles P. Tresser, Eugene Walach, David A. Weeshoff
  • Patent number: 7982490
    Abstract: Provided is a semiconductor integrated circuit including: an output circuit connected between a power supply (VDD0) and a ground (GND0), having an input connected to an input terminal, and having an output connected to an output terminal; and a power-supply-noise cancelling circuit connected between the input terminal and the output terminal to generate a current that cancels a current flowing from the power supply (VDD0) to the output terminal or a current flowing from the output terminal to the ground (GND0), based on a potential difference between the input terminal and the output terminal.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: July 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masashi Kurokawa, Kenichi Kawakami
  • Patent number: 7977185
    Abstract: A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: July 12, 2011
    Assignees: International Business Machines Corporation, Chartered Semiconductor Manufacturing Ltd.
    Inventors: Brian J. Greene, Chung Woh Lai, Yong Meng Lee, Wenhe Lin, Siddhartha Panda, Kern Rim, Young Way Teh
  • Patent number: 7979602
    Abstract: A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 7973560
    Abstract: A level shifter includes a first level shift circuit that converts a signal level of a first pulse signal into an amplitude level of a power supply voltage, and a second level shift circuit that converts a signal level of the second pulse signal into an amplitude level. Each of the first and second level shift circuits includes a first transistor of a first conductivity type having a gate receiving the first and second pulse signals respectively, a source connected to a ground, and a drain that outputs a level shifted pulse signal, and a second transistor of a second conductivity type having a gate connected to the first transistor gate, a drain connected to the first transistor drain, and a source connected to the power supply via a connected transistor group, the connected transistor group includes at least one of the second conductivity type transistors.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: July 5, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Kuge
  • Patent number: 7974872
    Abstract: A system (and method) assists consideration of selection that recommends selection candidates to a considerer who is considering selection in a certain field in order to assist determination of selection with which the considerer is satisfied. A question concerning the field is sent to a considerer and answer data is received from the considerer by the system. A degree-of-significance of each evaluation item in the field is estimated from the answer data. A degree-of-recommendation representing to which degree each selection candidate can be recommended to the considerer is calculated from evaluation data for each evaluation item with respect to each piece of selection candidate data in the field and the degree-of-significance of the considerer with respect to each evaluation item. Then, degrees of recommendation of selection candidate data in the field are presented to the considerer without change or after processing the data.
    Type: Grant
    Filed: July 23, 2002
    Date of Patent: July 5, 2011
    Inventors: Toshio Katayama, Tsukasa Makita
  • Patent number: 7969207
    Abstract: An input circuit, includes a first buffer circuit whose output is couple to an output signal terminal of the input circuit, and whose input is coupled to an input signal terminal of the input circuit, a second buffer circuit, a third buffer circuit, a first differential amplification circuit whose first input is coupled to a first external power source terminal, whose second input is coupled to an output of the second buffer circuit, and whose output is coupled to an input of the second buffer circuit, a second differential amplification circuit whose first input is coupled to a second external power source terminal, whose second input is coupled to an output of the third buffer circuit, and whose output is coupled to an input of the third buffer circuit, a first resistance whose one end is coupled to the output of the first differential amplification circuit, and whose another end is coupled between the input signal terminal of the input circuit and the input of the first buffer circuit, a second resistance
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 28, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuji Nakajima
  • Patent number: 7962427
    Abstract: A method and system for determining whether a sequence fragment g is atypical with respect to a reference sequence G using compositional methods and including constructing a template from G and g respectively containing a sequence of characters for a comparison with one another, wherein a number of characters contained in the template exceeds two. For the case where the sequences at hand are genetic, the atypicality detection can be used to determine whether a given sequence fragment g is the result of a horizontal transfer event.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: Aristotelis Tsirigos, Isidore Rigoutsos
  • Patent number: 7962258
    Abstract: A storing unit stores a map indicating correspondences between keywords representing states of a vehicle and faulty conditions of the vehicle. A keyword setting unit sets the keywords in response to the vehicle as a recorded object. A processing unit identifies the faulty condition corresponding to the set keywords by searching the storing unit. Then, the mode file corresponding to the identified faulty condition is decided as the mode file to be set in a data recording system, based on correspondences between the previously-set faulty conditions and data contents to be recorded and conditions.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: June 14, 2011
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Kiyoshige Noguchi
  • Patent number: 7958289
    Abstract: A method (and system) of storing information, includes storing main memory compressed information onto a memory compressed disk, where pages are stored and retrieved individually, without decompressing the main memory compressed information.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: Caroline Benveniste, Vittorio Castelli, Peter A. Franaszek
  • Patent number: 7956854
    Abstract: A display apparatus includes a display panel containing data lines; a driving circuit configured to generate a data signal in response to a first pixel data of k (k is an natural number) bits and to supply the data signal to one of the data lines; and a capacitor. A switch circuit connects or disconnects the data line to or from the capacitor in response to upper m bits (m is a natural number smaller than k) of the first pixel data.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshiharu Hashimoto
  • Patent number: 7954852
    Abstract: An object of the present invention is to markedly increase the tilt holding force of a tilt telescopic column. A tilt telescopic steering device includes: a fixed bracket 1 fixed to a vehicle; a movable bracket 2 capable of moving relative to the fixed bracket 1; an intermediate bracket 3 which movably supports the movable bracket 2 in an axial direction, is rotatably pivoted on the fixed bracket 1 and is provided with a bearing 301 for rotatably supporting a steering shaft 101; a lock shaft 4 for tiltably and telescopicably fixing the fixed bracket 1 and the movable bracket 2 at a predetermined position; and a connecting shaft 5 for telescopicably fixing the movable bracket 2 and the intermediate bracket 3.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: June 7, 2011
    Assignees: Honda Motor Co., Ltd., Yamada Manufacturing Co., Ltd.
    Inventors: Osamu Ueno, Takahiro Furuhashi, Naoyuki Takezawa, Minoru Takakusaki, Toshihito Osawa
  • Patent number: 7939843
    Abstract: A light emitting device has a light emitting element, and a high-refractive index layer that contacts an emission surface of the light emitting element. The high-refractive index layer has transparent fine particles uniformly arranged along the emission surface. The fine particles has a refractive index high than that of a material composing the emission surface of the light emitting element. Otherwise, a light emitting device has a light emitting element, a sealing material for sealing the light emitting element, and a high-refractive index layer that contacts an emission surface of the light emitting element. The fine particles has a refractive index high than that of a material composing the emission surface of the light emitting element and that of the sealing material. A phosphor may be included in the sealing material which is adapted to emit a wavelength-converted light by being excited by a light emitted from the light emitting element.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: May 10, 2011
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Takao Haruna, Akio Namiki, Mitsuhiro Inoue