Patents Represented by Attorney McGinn Intellectual Property Law Group, PLLC
  • Patent number: 8038561
    Abstract: A chain is provided with a plurality of links, and connecting members for connecting those links such that the links are relatively bendable to each other. A first pin of the connecting member is clamped between pulleys thereby to transmit the power between itself and said pulleys. The chain includes a central area with respect to chain width directions, and side areas located on the sides of the central area. In the central area, links adjoining in the chain width directions are pushed to contact with each other, and rotate relative to each other while exerting frictional forces on each other as the chain is bent. In each of the side areas, the links adjoining in the chain width directions are arrayed through a predetermined clearance.
    Type: Grant
    Filed: March 28, 2007
    Date of Patent: October 18, 2011
    Assignee: JTEKT Corporation
    Inventor: Shinji Yasuhara
  • Patent number: 8040995
    Abstract: A jitter detection circuit includes an oscillation circuit, a measurement period setting circuit for outputting a measurement period signal based on a measurement period specifying signal, the measurement period setting circuit receiving the output clock from a PLL circuit, a counter for counting the number of clock cycles output from the oscillation circuit over the period during which the measurement period signal is being output, a reference count value determining circuit for setting a reference count value for the number of clock cycles output from the oscillation circuit over the period during which the measurement period signal is being output, and an error detection circuit for detecting the jitter error of the PLL circuit based on the maximum count value and minimum count value counted by the counter, and the reference count value.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Nagayoshi Fukushima
  • Patent number: 8035365
    Abstract: A DC (direct current) converter includes a PWM (pulse width modulation) pulse generation unit outputting a PWM pulse signal whose duty ratio is controlled in accordance with an output voltage, a PFM (pulse frequency modulation) pulse generation unit outputting a PFM pulse signal whose pulse output interval is controlled in accordance with an output voltage, a selection circuit selecting and outputting any one of the PWM pulse signal and the PFM pulse signal in response to a selection signal, a drive circuit unit driving a load and generating an output voltage on the basis of a signal outputted from the selection circuit, and a switching control unit outputting the selection signal. When the selection signal is in a second state, the switching control unit detects a fact that the number of pulses of the PFM pulse signal in a measurement period increases to or above a set value of the maximum number of pulses, and switches the selection signal to a first state.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: October 11, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Hidehiro Kikuchi
  • Patent number: 8036921
    Abstract: A method (and system) of providing optimization repeatability in an on-demand computing environment removes variability in an optimization model instance and can be exemplarily implemented in a service architecture. The method and system receives a plurality of physical data instances, which are different representations of the same logical data model, and transforms the plurality of physical data instances into a normalized physical data instance, which can be combined with an optimization model to form a unique optimization model instance, thereby providing repeatability in solving optimization problems.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: October 11, 2011
    Assignee: International Business Machines Corporation
    Inventors: Tarun Kumar, Gyana R. Parija, Haifeng Xi
  • Patent number: 8033793
    Abstract: The present invention provides an impeller in which a metallic bush can be inserted correctly into a synthetic resin impeller main body manufactured by resin molding using a die, and a determination as to whether or not the impeller has been manufactured correctly can be made easily. The impeller comprises: a metallic bush comprising a circumferential boss portion having a substantially truncated cone-shaped throttle portion positioned on a front surface axial end side, a periaxial support boss portion positioned in an axial center, and a circumferential protruding portion positioned on a back surface axial end side; and an impeller main body made of synthetic resin and formed with a V-shaped bulging portion that bulges axially in the center of a front surface side of a disk-shaped vane portion fulcrum, in which a plurality of vanes are formed integrally on the periphery of the V-shaped bulging portion.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: October 11, 2011
    Assignees: Sigma Co., Ltd., Yamada Manufacturing Co., Ltd.
    Inventors: Kazuo Ikeda, Yasutaka Okuda, Ryouhei Adachi, Satoshi Maruyama, Satoshi Hoshino
  • Patent number: 8029351
    Abstract: As a result of lottery using the roulette device 3, if the ball 27 enters in the bonus pocket 24 among the pockets formed on the wheel 22, the special bonus game using the WIN lamp 11 occurs and all credits betted to each station 4 in the present game are paid out (S15) to one station 4 which is determined based on the lottery (S123) by the server control CPU 81 that winning is obtained.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: October 4, 2011
    Assignee: Universal Entertainment Corporation
    Inventors: Toshihiko Kosaka, Junichi Kogo, Kazumasa Yoshizawa, Yoichi Kato
  • Patent number: 8026756
    Abstract: A voltage reference circuit is provided with: an operational amplifier circuit; first and second resistor elements; first and second diodes; and first and second transistors. The first resistor element and the first diode are connected in series between a first input terminal of the operational amplifier circuit and a reference level node. The second resistor element and the second diode are connected in series between a second input terminal of the operational amplifier circuit and the reference level node. The first transistor is connected between a power supply node and the first input terminal of the operational amplifier circuit and has a control electrode receiving an output of the operational amplifier circuit. The second transistor is connected between the power supply node and the second input terminal of the operational amplifier circuit and has a control electrode receiving the output of the operational amplifier circuit. The value of R12·ln(n11·n22)/(R12·n12·R11) is adjusted to approximately 23.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: September 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Tachio Yuasa
  • Patent number: 8027948
    Abstract: A method of generating an ontology includes determining plural concepts from a data set by using a first predetermined pattern, using a second predetermined pattern to determine a relationship between the plural concepts, and between a concept and a concept token in the plural concepts, and generating the ontology based on the relationship.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Rama Kalyani Akkiraju, Richard T. Goodwin, Hui Guo, Anca-Andreea Ivan
  • Patent number: 8023573
    Abstract: A wireless communication system according to an exemplary aspect of the present invention is a wireless communication system which performs wireless communications between a first wireless communication device and a second wireless communication device, wherein the first wireless communication device includes: a delay profile calculation unit for calculating a delay profile by calculating a correlation value for a received signal; a valid path detection unit for detecting a valid path using the delay profile and forcibly detecting a valid path when there is no path satisfying a condition of the valid path; and a forcible valid path notification unit for notifying that the valid path is forcibly detected.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: September 20, 2011
    Assignee: NEC Corporation
    Inventor: Shingo Kikuchi
  • Patent number: 8023603
    Abstract: An interface circuit includes a detector to detect a particular pattern from a sequence of output data, a shift clock generator to change a cycle of a shift clock according to the detection result, a shift register section to change a data output width by the shift clock and output it as drive data, and an open-drain output section including an N-channel transistor driven by the drive data and a pull-up resistor. The detector detects a sequence where the current output data is “0” and the next output data is “1”, and the shift clock generator shortens and extends the cycles of the shift clock corresponding to “0” and “1”, respectively.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Toshiyuki Kumagai
  • Patent number: 8024614
    Abstract: A debugger includes: a break detecting circuit which, when the state of a microprocessor core corresponds to a previously set condition, generates a break request signal for requesting a transition of the microprocessor core to a debug state; a trigger detecting circuit which, when a predetermined signal of additional hardware corresponds to a previously set condition, generates a trigger request signal for requesting observation of the predetermined signal; and, an execution control circuit which, when the trigger request signal has been transmitted, outputs a trigger signal for observing the predetermined signal by means of a logic analyzer and outputs a break signal for causing the microprocessor core to transition to the debug state.
    Type: Grant
    Filed: July 4, 2007
    Date of Patent: September 20, 2011
    Assignee: NEC Corporation
    Inventor: Kouhei Nadehara
  • Patent number: 8022403
    Abstract: A semiconductor apparatus has a light-receiving element. The light-receiving element has a photodiode unit having a shield film for removing noise, at least two test pads, and a shield film pseudo pattern which is formed by the same membranous type as the shield film and connected to the two test pads. The photodiode unit and the shield film pseudo pattern are integrated in one semiconductor chip. A resistance value of the shield film pseudo pattern is measured using the test pads connected to the shield film pseudo pattern. CMR of a photocoupler can be evaluated according to the correlation relationship between the measurement result and the sheet resistance of the shield film.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Tomohiko Matsumae
  • Patent number: 8020133
    Abstract: A semiconductor integrated circuit according to an embodiment of the invention includes a single-cut via 60 and a multi-cut via 30 that includes a first via 30a and a second via 30b. An overhang (OHa or OHb) with respect to at least one of the first via 30a and the second via 30b is smaller than an overhang OH with respect to the single-cut via 60.
    Type: Grant
    Filed: March 20, 2008
    Date of Patent: September 13, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Keiichi Nishimuda
  • Patent number: 8014212
    Abstract: Disclosed is a memory circuit that includes a plurality of columns of bit line pairs, each bit line pair including True and Bar bit lines, between which at least a memory cell is connected; a sense amplifier that has True and Bar terminals and that performs differential amplification; and a switching circuit that selects one of: a straight connection in which the True and Bar bit lines of a selected column bit line pair are connected to the True and Bar terminals of the sense amplifier, respectively; and a cross connection in which the True and Bar bit lines of a selected column bit line pair are connected to the Bar and True terminals of the sense amplifier, respectively.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Shunya Nagata
  • Patent number: 8015462
    Abstract: A test circuit including a TAP controller specified in IEEE (Institute of Electrical and Electronics Engineers) 1149 and a test access port includes a first controller including a selecting circuit and a first TAP controller, the selecting circuit generating an internal TMS signal in accordance with TMS signal and selecting an output destination of the internal TMS signal in accordance with a selection signal, and the first TAP controller changing internal state based on the internal TMS signal, testing corresponding test target block in accordance with instruction code for test, and generating the selection signal in accordance with instruction code for selection, and a second controller including a second TAP controller changing internal state based on the internal TMS signal and testing corresponding test target block in accordance with the instruction code for test.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Nakamura, Toshiharu Asaka, Toshiyuki Maeda, Tomonori Sasaki
  • Patent number: 8015043
    Abstract: A method of forecasting workforce demand, includes forecasting an ongoing engagements demand, forecasting an opportunities demand, forecasting a wedge engagements demand, representing a result of the forecasting the ongoing engagements demand as a first workforce demand statement, a result of the forecasting the opportunities demand as a second workforce demand statement, and a result of the forecasting the wedge engagements demand as third workforce demand statement, and integrating the first workforce demand statement, the second workforce demand statement and the third workforce demand statement to generate an overall workforce demand forecast.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 6, 2011
    Assignee: International Business Machines Corporation
    Inventors: Heng Cao, Mark A. Eaton, Meng-Chen Hsieh, Jianying Hu, Ta-Hsin Li, Bonnie Kathryn Ray
  • Patent number: 8005997
    Abstract: A monitoring device according to the present invention is a monitoring device connectable between a target device including a first memory holding a first data sequentially renewed and a host device acquiring a second data coinciding with the first data held in the first memory, and includes a first bus, a second memory holding the second data, a first control portion allowing the second data to be sequentially inputted to the second memory through the first bus according to the renewal of the first data, an event detection portion outputting an event detection signal when the data flowing to the first bus satisfies an event detection condition set in advance, and a second control portion allowing the second data to be outputted from the second memory based on the event detection signal.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: August 23, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Susumu Hirai
  • Patent number: 8004537
    Abstract: A color correction apparatus includes a correction unit to correct a color of an input pixel having a color included in a specified region of a color space, a correction range selector to select a range with a center in a grayscale to the specified region. With this color correction apparatus, a grayscale can be specified as the target color and only a part of a region in white component direction can be set as the correction range. Thus a desired range of the grayscale can be corrected.
    Type: Grant
    Filed: March 8, 2007
    Date of Patent: August 23, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhiro Fuji
  • Patent number: 7999876
    Abstract: A pull-down detection apparatus includes a pixel comparator at least performing pixel comparison between a subsequent field and a present field and horizontal pixel comparison in the subsequent field and the present field to determine a presence of a pixel change between the subsequent field and the present field, a field comparator determining a presence of an image change between the subsequent field and the present field based on a determination result in the pixel comparator, and a pull-down determinater determining that the input video signal is generated by pull-down processing based on a history of a determination result in the field comparator.
    Type: Grant
    Filed: February 10, 2006
    Date of Patent: August 16, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuhiro Fuji
  • Patent number: 8000019
    Abstract: An optical system for a display panel is disclosed. An optical system comprises a color separating portion for separating light that is emitted from a light source into a plurality of beams having different spectra; and a projecting portion for projecting the plurality of beams onto a plurality of divided areas of a predetermined range in the display panel, while sequentially switching the plurality of beams.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: August 16, 2011
    Assignee: NEC Viewtechnology, Ltd.
    Inventor: Atsushi Kato