Abstract: Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads.

Abstract: A wrapped-gate transistor includes a substrate having an upper surface and first and second side surfaces opposing to each other. Source and drain regions are formed in the substrate with a channel region therebetween. The channel region extends from the first side surface to the second side surfaces of the substrate. A gate dielectric layer is formed on the substrate. A gate electrode is formed on the gate dielectric layer to cover the channel region from the upper surface and the first and second side surfaces with the gate dielectric therebetween. The substrate is a silicon island formed on an insulation layer of an SOI (silicon-on-insulator) substrate or on a conventional non-SOI substrate, and has four side surfaces including the first and second side surfaces. The source and drain regions are formed on the portions of the substrate adjoining the third and fourth side surfaces which are perpendicular to the first and second side surfaces.

Abstract: Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Qcrit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated circuits are scaled to smaller sizes and manufactured at increased integration densities. Formation of the added capacitance as deep trench capacitors avoids any constraint on circuit or memory cell layout. Degradation of performance is avoided and performance potentially improved by permitting alteration of proportions of pull-down and pass gate transistors in view of the increased stability imparted by the added capacitors. One of the capacitor electrodes is preferably shorted to the supply voltage through an impurity well. Thus, the memory cell size can be reduced while greatly reducing susceptibility to soft errors; contrary to the effects of scaling at current and foreseeable feature size regimes.

Abstract: A fast DRAM memory uses ground-sensing as opposed to traditional Vdd/2 sensing. A selected DRAM cell connects to a bit-line true (BLT) or a bit-line complement (BLC). At the start of each cycle the BLT and BLC are restored to ground potential. A pair of alternating reference cells are provided for each bit-line. When a selected DRAM cell is connected either BLT or BLC the first reference cell in the pair is connected to the other bitline to provide a reference voltage to the other bitline which can be compared to the voltage provided by the selected DRAM cell. On a subsequent cycle using the same bitline the second reference cell in the pair is used. Thus it is not necessary to wait for the first reference cell to recharge prior to beginning the next cycle. Switching between the first and second reference cells in the pair alternates in this manner resulting in faster cycle time.

Abstract: According to one aspect of the present invention, the thin film transistor array substrate basically includes a gate line assembly based on an Ag alloy. The Ag alloy comprises Ag and at least one of alloy elements and the alloy elements each bearing a low melting point. The gate line assembly comprises a gate electrode and a gate line. A data line assembly crosses over the gate line assembly while being insulated from the gate line assembly. The data line assembly comprises a source electrode, a drain electrode and a data line. A semiconductor layer contacts the source electrode and the drain electrode. The semiconductor layer forms a thin film transistor together with the gate electrode, the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode.

Abstract: A method for removing surface oxide from polysilicon includes depositing a very thin layer of germanium (e.g. monolayers in thickness) over the polysilicon immediately before a subsequent polysilicon deposition step, and then heating the germanium-coated polysilicon in a vacuum to sublime (remove) volatile germanium oxide. This method is applied to formation of a trench capacitor, which uses either doped amorphous silicon or doped amorphous SiGe material in the formation of the electrodes.

Abstract: The present invention relates to a method for recycling an alignment layer material. The recycled alignment layer material shows the same characteristics as an original alignment layer material. The waste solution of the alignment layer material produced during the liquid crystal display manufacturing processes is recycled by solidifying polyamic acids and soluble polyimides by putting a waste solution of the alignment layer material into an organic solution or ultra purified water in which the alignment layer material constituents of polyamic acids and soluble polyimides are insoluble, separating polyamic acids and soluble polyimides from the organic solvent or ultra purified water, and dissolving the separated solid polyamic acids and soluble polyimides into a solvent. Recycling the alignment layer material in this method can significantly reduce the manufacturing costs.

Abstract: The data destruction machine is a desk-top, portable unit with a short (under 10 second) cycle time, pluggable into a wall outlet. Upon insertion of a CD into the machine, which is fully automatic, data is erased, and the cleaned CD is ejected. The machine converts the data-storage layer into residue consistent with security destruction standards from which no data is retrievable.

Abstract: A PLL circuit includes a comparator, an integrator, a phase controller, a current control oscillator and a feedback frequency divider. The comparator compares a phase of an input signal with a phase of a feedback signal to generate a comparison result. The integrator generates a first current to control an oscillation frequency of an output signal based on the comparison result. The phase controller controls a phase of the output signal based on the comparison result such that a phase difference between the phase of the input signal and the phase of the output signal at a lock state is reduced to generate a second current. The current control oscillator generates the output signal. The output signal oscillates at a frequency corresponding to a third current, wherein the first current and the second current add up to the third current. The feedback frequency divider performs a frequency division on the output signal to generate the feedback signal to send to the comparator.

Abstract: Disclosed herein is a printed circuit board comprising a ground layer and a signal layer in which the characteristic impedance of a specific source line is made to be not less than three times as large as the impedance at an upper limit frequency at which the electromagnetic wave radiation of a specific capacitor may occur. In this printed circuit board, variation of a power source voltage and unnecessary electromagnetic wave radiation can be suppressed.

Abstract: The invention provides a speech recognition apparatus which makes it possible to utilize, upon prior learning, in addition to SD-HMMs of a large number of speakers, adaptation utterances of the speakers to make operation conditions coincide with those upon speaker adaptation to allow prior learning of parameters having a high accuracy and by which, also when the number of words of adaptation utterances upon speaker adaptation is small, adaptation can be performed with a high degree of accuracy.

Abstract: An electronic scale integrally formed within the housing of a piece of office equipment increases a user's work space in a home or business environment. The piece of equipment may be a personal computer or one of its peripheral devices. A mailing system automatically computes postal and/or private carrier rates for items of mail based on weight signals derived from the electronic scale. Since the scale is integrated into the computer, all mailing tasks are performed at a user's desk using the least space possible. The system is performed in accordance with a computer program which steps a user through the postage-computing method using one or more interactive display screens.

Abstract: The present invention provides a method of rapidly screening ligands on the basis of their binding affinity and binding enthalpy by carrying out binding assays at a minimum of two temperatures. This technique permits the selection for further optimization of lead ligands that bind to the target molecules with favorable enthalpies. Those ligands will exhibit higher solubilities in aqueous solution than ligands selected by conventional means, and may exhibit lower susceptibilities to resistant mutations. The method may be utilized as a standalone technique, or may be adapted to, for example, known high throughput screening technologies. The present invention further comprises an apparatus for carrying out the described methods.

Abstract: In a digital demodulation apparatus, a first signal generating circuit generates a first clock signal and a first frame signal which are always in an active state, and a second signal generating circuit generates a second clock signal and a second frame signal which are intermittently in an active state. An analog-to-digital converter converts an intermediate analog signal into a digital signal. A smoothing digital filter performs a smoothing operation upon the digital signal in synchronization with the first clock signal and the first frame signal to general parallel data. A data phase synchronization circuit converts the parallel data into serial data in synchronization with the second clock signal and the second frame signal. A digital signal processing circuit performs a signal processing operation upon the serial data in synchronization with the second clock signal and the second frame signal.

Abstract: An automated inspection system particularly adapted for detection and discrimination of surface irregularities of specularly reflecting and other materials, such as are employed in laminate chip carriers and printed circuit boards, includes an area scan image sensor allowing illumination sources to surround an area of a surface being inspected. The illumination source preferably provides either or both bright field and dark field illumination of the surface; developing generally complementary images of surface irregularities. A self-registering rules-driven process for developing inspection masks reduces alignment operations and improves performance. Image enhancement and morphological operations to detect surface irregularities are performed by digital signal processing, preferably using a dedicated vision processor. Masks screen potential defects to critical mounting and bonding surfaces accurately without requiring alignment of data or reference images to acquired images.

Abstract: A dispersion compensating device for compensating dispersion of signal light. In an optical fiber communication system, distortion of optical pulse waveform caused by wavelength distortion is compensated. The signal light is inputted through an input port, propagating through a dispersion compensating fiber through a port of an optical circulator. The signal light is reflected by a totally internal highly reflective surface, again propagating through the dispersion compensating fiber reciprocally, thus being outputted through an output port of the optical circulator. Since the signal light propagates through the dispersion compensating fiber reciprocally, the dispersion compensating fiber is capable of compensating dispersion with one-half the length of the conventional example.

Abstract: The process for detection and for quantitative determination of substances emitted or perspired through the skin is derived from flow diffusion analysis. The measuring system conceived for this purpose uses a diffusion half cell through which an acceptor medium flows and which is closed by a membrane. For the duration of the measurement, the membrane is brought into contact with the skin or a closed gas volume formed over the skin. With the process and the related measuring system, the blood alcohol level can be determined with a good degree of precision indirectly via the quantity of (gaseous) ethanol emitted through the skin.

Abstract: A tracking assembly for mounting to a support frame of a conveyor belt installation in order to keep the conveyor belt which travels thereon centrally aligned includes a sub-frame adapted to be mounted to a support frame of a conveyor belt installation. A plurality of independently rotatable idlers are mounted for rotation on the sub-frame to support the conveyor belt of the installation in position. The idlers are aligned generally parallel to each other spaced apart from each other across the width of the belt, with the sub-frame and idlers being mounted to the support frame generally transverse to the length of the belt. Each of the idlers include a support shaft, an outer drum rotatably supported on the shaft, and a pivot assembly located within the drum defining a pivot axis about which the drum is pivotable relative to the shaft, the pivot axis being perpendicular to the belt which in use travels on the idler.