Abstract: A shut-off circuit included in a dynamic flip-flop isolates output terminals of the dynamic flip-flop from circuitry within the flip-flop that could introduce noise on either output terminal during a portion of the evaluation phase. Since the output terminals are isolated from the input terminals during this portion of the evaluation phase, spurious input signals have no affect on the output signal levels. Similarly, charge within the dynamic flip-flop that is not completely dissipated in the transition from a precharge phase to the evaluation phase has no affect on the output signal levels during this portion of the evaluation phase.

Abstract: A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe.

Abstract: A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots as the results buffer, each slot in the condition code buffer in one-to-one correspondence with a slot in the results buffer. Each live instruction in the processor is assigned a slot in the results buffer and the condition code buffer. Each speculative result produced by the execution units is stored in the assigned slot in the results buffer. When an instruction is retired, the results for that instruction are transferred to an architectural result register and any condition codes generated by that instruction are transferred to an architectural condition code register.

Abstract: To fabricate a flip-chip micromachine package, a micromachine chip is mounted as a flip chip to a substrate. The micromachine chip is attached such that a micromachine area on a first surface of the micromachine chip faces the substrate. A limited flow liquid encapsulant is dispensed around the micromachine chip and cured to form a package body. The micromachine chip, the package body, and the substrate define a sealed cavity. The micromachine area is located within the sealed cavity and protected from the ambient environment.

Abstract: A collet assembly coupled to a rotary-linear drive unit allows easily placement of a susceptor shaft within a collet of the collet assembly when the collet assembly is in a first position. After the susceptor shaft is placed into the collet, the collet assembly is retracted to a second position by a spring force acting on a collet draw bar that is coupled to the collet. As the collet assembly is retracted by the spring force, the collet is closed about the susceptor shaft by the interaction between the collet and a collet spindle in which the collet is moveably mounted. As the collet closes, the collet assembly exerts a pressure about a circumferential surface of a susceptor shaft that in turn holds the susceptor shaft firmly in place within the collet, i.e., holds the susceptor shaft stationary within the collet. Consequently, when the susceptor shaft is rotated by the rotary-linear drive unit, there is no wobble associated with the rotary movement of the susceptor shaft.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines.

Abstract: A self-aligning mating structure of a substrate support element is connected to an alignment guide. The combination of the self-aligning mating structure and the alignment guide assures that the element properly seats in a complementary mating structure shaped opening in a susceptor as the susceptor is moved into the processing position. An end of the substrate support element opposite to and removed from the self-aligning mating structure is weighted. Thus, the substrate support element remains properly seated in the susceptor throughout the process cycle. The end of the substrate support element opposite to and removed from the self-aligning mating structure also includes a support structure. As the susceptor is lowered from the processing position to the load/unload position, the support structure contacts the bottom of the reaction chamber or other surface in the reaction chamber.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: A control block clock distribution network includes a logic circuit, one or more nth-level buffers, and a (n-1)th-level buffer that drives the one or more nth-level buffers. The logic circuit includes a predefined area containing substantially only clocked logic elements. The number of clocked logic elements in the predefined area is constrained to be less than or equal to a predetermined maximum number. The one or more nth-level buffers are located within the predefined area, whereas the (n-1)th-level buffer is located outside of the predefined area. Each nth-level buffer receives the clock signal outputted by the (n-1)th-level buffer and provides a clock signal to a predetermined number of the clocked logic elements within the predefined area Because the predefined area has known dimensions, the length of the clock line from the (n-1)th buffer to the nth-level buffers is known to within a range.

Abstract: An I/O command block, that is stored in a memory, includes information for connecting the I/O command block to other I/O command blocks in a chain structure. The I/O command block chain structure allows simultaneity of execution, provides a mechanism to inhibit and enable execution of an individual I/O command block, and a mechanism for establishing precedence in the sequence of execution of the I/O command blocks. This level of capability is provided by only information in the I/O command blocks within the chain. A method for specifying concurrent execution of a string of I/O command blocks stored in a memory using only information in the string of I/O command blocks allows concurrent execution of a plurality of I/O commands. The method first configures one I/O command block in the string as a head of string concurrent I/O command block. Another I/O command block in the string is configured as an end of string concurrent I/O command block. The remaining I/O command blocks, i.e.

Abstract: A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.

Abstract: A novel rapid thermal process (RTP) reactor processes a multiplicity of wafers or a single large wafer, e.g., 200 mm (8 inches), 250 mm (10 inches), 300 mm (12 inches) diameter wafers, using either a single or dual heat source. The wafers or wafer are mounted on a rotatable susceptor supported by a susceptor support. A susceptor position control rotates the wafers during processing and raises and lowers the susceptor to various positions for loading and processing of wafers. A heat controller controls either a single heat source or a dual heat source that heats the wafers to a substantially uniform temperature during processing. A gas flow controller regulates flow of gases into the reaction chamber. Instead of the second heat source, a passive heat distribution is used, in one embodiment, to achieve a substantially uniform temperature throughout the wafers. Further, a novel susceptor is used that includes a silicon carbide cloth enclosed in quartz.

Abstract: A multi-level cache and method for operation thereof is presented for processing multiple cache system accesses simultaneously. The cache includes a first non-blocking cache receiving data access requests from a device in a processor, and a first miss queue storing entries corresponding to data access requests not serviced by the first non-blocking cache. A second non-blocking cache is provided and receives data access requests from the first miss queue, and a second miss queue stores entries corresponding to data access requests not serviced by the second non-blocking cache. A first arbiter arbitrates between two or more access requests to the first non-blocking cache. A second arbiter can be provided to arbitrate between two or more access requests to the second non-blocking cache.The arbiter is capable of determining if an anticipatory stall signal should be asserted if any of the cache resources, such as a queuing structure, is becoming overloaded.

Abstract: A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.

Abstract: Embodiments of the present invention provide a stack renaming method and apparatus for stack based processors. Using principles of the present invention, a stack can be accessed simultaneously by one or more functional units in a stack processor. The stack apparatus includes a stack renaming unit capable of renaming a logical stack address to a real stack address. Each logical stack address corresponds to a storage element in the stack renaming unit which stores a real stack address. A circular counter is used in the stack renaming unit to sequentially cycle through each of the logical stack addresses. The real stack addresses corresponding to each of the logical stack addresses can be stored out of order in the stack renaming unit. A stack control unit is coupled to the stack renaming unit and provides one or more control signals to the stack renaming unit and coordinates the operation of the stack renaming unit within the stack apparatus.

Abstract: The present invention provides a unique multi stack memory system to provide access to multiple portions of the method frames of a stack based computing system. In one embodiment of the invention, a multi-stack memory system includes a first stack configured to store a first frame component of a first method frame and a second frame component of a second method frame. A second stack is configured to store a second frame component of the first method frame and a first frame component of second method frame. The first frame component of the method frames can be for example an operand stack. The second frame components of the method frames can be, for example, arguments and local variable areas.

Abstract: To reduce p-n junction leakage at the boundary between lightly doped wells formed in lightly doped bulk materials, a high concentration region is implanted at the junction. The high concentration region contains a relatively high dopant level, and thus reduces the width of the depletion region at the junction. The reduced width of the depletion region in turn reduces junction leakage.

Abstract: In executing a new method, a hardware processor loads the execution environment on a stack in the background and indicates what portion of the execution environment has been loaded so far, e.g., simple one bit scoreboarding. Thus, the hardware processor tracks the information in the execution environment loaded on the stack. The hardware processor tries to execute the bytecodes of the called method as soon as possible, even though the stack is not completely loaded. If accesses are made to variables already loaded, overlapping of execution with loading of the stack is achieved. Thus, execution and loading continue until information in the execution environment needed for the execution is not on said stack as indicated by said tracking.

Abstract: A method for making an asymmetric MOS device having a notched gate oxide is disclosed herein. Such MOS devices have a region of a gate oxide adjacent to either the source or drain that is thinner than the remainder of the gate oxide. The thin "notched" region of gate oxide lies over a region of the device's channel region that has been engineered to have a relatively "high" threshold voltage (near 0 volts) in comparison to the remainder of the channel region. This region of higher threshold voltage may be created by a pocket region of increased dopant concentration abutting the source or the drain (but not both) and proximate the channel region. The pocket region has the opposite conductivity type as the source and drain. A device so structured behaves like two pseudo-MOS devices in series: a "source FET" and a "drain FET." If the pocket region is located under the source, the source FET will have a higher threshold voltage and a much shorter effective channel length than the drain FET.

Abstract: A cache system including a data cache memory comprising a plurality of cache lines. A tag store has an entry representing each line in the cache memory where each entry comprises tag information for accessing the data cache. The tag information includes state information indicating whether the represented cache line includes dirty data. A speculative write back unit monitors the state information and is operative to initiate a write back of a cache line having more than a preselected amount of dirty data.