Abstract: The specification discloses a package for a large number of integrated circuits. The package includes a top piece and a bottom piece formed of crystalline silicon with two levels of conductor regions formed in the top and bottom pieces. The integrated circuits are placed vertically between the top and bottom pieces and are held to the top and bottom pieces by high temperature adhesives. Solder balls which are placed on integrated circuits after the fabrication of the integrated circuits are then heated to cause the solder balls to reflow onto their respective connectors in the top and bottom pieces. TAB type conductors are then connected to the top and bottom pieces so that the integrated circuit held within this embodiment of the present invention may be connected to other circuitry.

Abstract: A method for forming a BICMOS device having MOS devices and bipolar devices formed during the same process includes the steps of first forming bipolar and MOS regions and then patterning gate electrodes in the MOS regions to define source/drain regions on either side thereof. A layer of oxide is formed over the bipolar transistor region which has an intrinsic base defined therein. The oxide is patterned to form an opening for an emitter and an opening for an extrinsic base, the opening separated by a layer of oxide. The refractory metal is then sputtered over the substrate and a silicide layer forms in the emitter and base regions of the bipolar transistor and the source/drain regions of the MOS transistors.

Abstract: A CMOS output buffer is disclosed, which provides ESD protection by incorporating a low resistance path within the p-channel pull-up device. Output buffers according to the prior art can be damaged by ESD occurring at the output terminal having a positive polarity, as the drain-to-substrate diode of the pull-down transistor breaks down in the reverse-bias direction, especially when second breakdown occurs. The p-channel pull-up device, formed within an n-well, is fabricated to have n-type diffusions disposed near to the p-type drain diffusions. The distance between the n-type diffusion and the drain diffusions in the pull-up device reduces the series "on" resistance of the drain-to-n-well diode of the pull-up device, to a level which keeps the voltage at the output terminal below the reverse-bias breakdown voltage of the drain-to-substrate diode in the pull-down device. The pull-up device may be constructed in a ladder structure to facillitate the reduction of this resistance.

Abstract: In order to compare the total reached by a counter counting pulses from a source with a given number, the more significant digits from the counter are compared with the corresponding digits of the given number. The comparator produces an output when the groups of more significant digits are equal. An adjusted output taking account of the less significant digits of the given number is obtained by delaying the output by a time period equal to that required for the number of pulses from the source to be incremented by the number represented by the less significant digits of the given number. The time delay is provided by a multi-stage shift register using the pulses from the source as shift pulses, the output from the comparator being applied to the first stage and the adjusted output being derived from a stage selected according to the less significant digits of the given number.

Abstract: Disclosed is a bipolar-CMOS circuit which includes a NMOS transistor site (18) electrically isolated from a bipolar transistor site (16). The NMOS transistor site (18) includes a semiconductor region (24) isolated from a bipolar transistor well (26) by deep diffusion ring (32). A buried layer (13) forms a bottom of the deep diffusion isolation ring (32). A backgate voltage can be applied to the isolated semiconductor region (24) of the NMOS device, which bias may be different than that applied to the substrate (10). Optimum performance of the NMOS transistor is thus assured irrespective of the magnitude of operating voltage of the bipolar transistor.

Abstract: A system and method for testing the continuity of interconnecting nets on a substrate to be used in multi-chip technology is provided. The system includes coupling a test pad (15) to the net (12) to be tested. The test pad (15) is coupled through a diode (34) to a common node (32). The voltage of a first node (16) of the net (12) is sensed by a voltmeter (38) which is coupled to ground. A predetermined current signal is applied to each node (16, 18, 20, 22) in the net through the use of a probe (42). The voltage of the remaining nets (14) is sensed by a voltmeter (44). If an erroneous interconnection (31) is present between the net (12) to be tested and any other net (14) on the substrate, the voltage of the other net (14) will fluctuate. The voltmeter (38) will indicate if there is an electrical connection between the node (16) and the test pad (15) during testing.

Abstract: An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shaped drain region (16), with at corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (P1A). This floating gate channel section (32a/P1A) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the coresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD).

Abstract: Disclosed is a device power supply in a semiconductor test system for supplying programmed test pattern voltages to a semiconductor device under test and for current range switching of current range resistors without effecting the output voltage of the device power supply.

Abstract: A tunneling device (50) with the emitter (62) to collector (58) current transported by resonant tunneling through a quantum well (52) and controlled by carriers injected into the well (52) from a base (60) is disclosed. The injected carriers occupy a first energy level in the well (52) and the resonant tunneling is thorough a second energy level in the well (52) thereby separating the controlled carriers from the controlling carriers. AnotherThree-terminal tunneling devices using three different bandgap semiconductor materials to segregate controlling carriers from controlled carriers are disclosed.

Abstract: A pressure transducer having a capactive pressure sensing moudle disposed in a housing is biased against a sealing ring disposed in a chamber circumscribing a fluid pressure inlet by a retainer ring mounted in the housing. A selected back-up washer may be used to accommodate various size pressure sensing modules. The housing is sealed from the environs by means of a hermetic glass-to-metal header which mounts terminals to provide electrical coupling to electronics mounted in the housing.

Abstract: According to the invention, an integrated circuit with improved capacitive coupling is provided, and includes a first conductor (20), a second conductor (16), and a third conductor (22). The second conductor (22) and third conductor (16) are disposed adjacent each other, separated by an insulator region (60). The first conductor (20) contacts the third conductor (16) and extends across a portion of the third conductor (22). The first and third conductors are separated by an insulator region (54). A voltage applied to first conductor (20) and second conductor (16) is capacitively coupled to third conductor (22).

Abstract: A fuel supply device and heating device or system for an electrically controlled fuel injection engine has an air intake and a fuel injector arranged to direct air and fuel respectively into a cylinder inlet passageway leading to a cylinder inlet valve opening in an engine cylinder and has a heating device located in the passageway having a heating surface arranged to receive fuel from the fuel injector for heating the fuel and deflecting it or directing it into the cylinder through the cylinder inlet valve opening substantially free of condensing contact with walls of the passageway, thereby to assure that the proper ratio of air and fuel as provided by the electronic controls of the engine are properly received in the engine cylinder.

Abstract: The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area.

Abstract: The invention provides an integrated circuit capacitor with a silicided polysilicon electrode (which silicide has not been used as an etch stop) as a bottom plate and a metal layer as a top plate. Subsequent to the formation of a patterned polysilicon layer, a multilevel dielectric is formed, and a via is etched therethrough to a polysilicon capacitor bottom plate. Then the polysilicon bottom plate is clad with a refractory metal silicide. The capacitor dielectric is then deposited, such a dielectric preferably consisting of an oxide/nitride layered dielectric. Contacts are etched to diffusion and to polysilicon electrodes as desired, and metal is deposited and patterned to form the top electrode of the capacitor over the capacitor dielectric, and to make contact as desired to diffusion and to polysilicon. This provides an improved silicide layer in the capacitor, as compared to processes which etch through oxide down to the silicide, and thus are using the silicide as an etch stop.

Abstract: An electrothermal sensor is shown having an electrically conductive substrate, an electrically insulating layer disposed on the substrate, a first thermistor disposed on a central region of the electrically insulating layer, a second thermistor disposed adjacent an edge of the electrically insulating layer, an electrical coupling device on the electrically insulating layer for coupling the first and second thermistors externally of the electrically insulating layer and a pair of electrical connecting devices coupled to the substrate and passing through the electrically insulating layer, the first thermistor being disposed between the pair of electrical connecting devices.

Abstract: A method and film/interconnect lead combination for attaching a plurality of sets of interconnect leads on a strip of film using an adhesive which loses bonding strength upon being exposed to energy such as heat or ultra violet light. The film holds the interconnect leads firmly in their proper position for bonding to an integrated circuit chip and to a leadframe or substrate such as a printed wiring board or a ceramic substrate for hybrid circuits. Either during or after bonding the interconnect leads to the leadframe or substrate, energy is applied to the adhesive holding the interconnect leads to the film and the film is detached from the interconnect leads in a manner which will not damage the leads due to the reduced adhesive strength. Thus, the leadframe package will not enclose the film.

Abstract: A quasi-interdigitated transistor (50) for rf power applications has a plurality of channel regions (102-118) that are each offset from each other in a y-direction such that a q.sub.x heating component from adjacent channel regions will affect any one channel region to a lesser extent than the q.sub.x from adjacent channel regions in the conventional interdigitated structure. In a preferred embodiment, the channel regions (102-118) are formed in a single, curved, V-shaped row such that the cumulative transverse width of all of the transistor sections is less than the waveguide cutoff frequency. The V-shaped row of transistor sections also provides the advantage of parallel signal paths having approximately the same propagation time delay such that there is no phase cancellation within the device.

Abstract: A non-volatile memory is provided which provides a floating gate (42) disposed over control gate (38) in order to increase the coupling therebetween. The degree of coupling may be varied by adjusting the area of the floating gate formed over the control gate relative to the area of the floating gate over the substrate.

Abstract: A bipolar transistor formed in a trench depression such that a single impurity diffusing step is effective to form a buried collector layer electrically connected to a vertical collector conductor. The lateral diffusion forming the vertical collector conductor is effective to form the conductor with a uniform vertical doping profile, thereby reducing non-uniform series collector resistance characteristics. A trench depression sidewall dielectric is formed, and the trench is filled with a transistor silicon material by a selective epitaxial process. Base and emitter region are then formed in the collector epitaxial material.

Abstract: A three pole relay is shown which operates in response to the flow of normal operating current across fluorescent lamps to energize a coil which actuates a relay to open switches disposed in all of the filament lines associated with the lamp to shut off filament current while maintaining current flow across the lamps themselves.