Abstract: Monolithic gallium arsenide limiters (30) formed of p-i-n diodes (32, 34) that are distributed devices between conductors of coplanar waveguide sections (40, 42, 44) are disclosed. The diode doped regions underlie the coplanar conductors and the diode intrinsic region underlies the coplanar waveguide gap. The grounded coplanar segments connect to a backside ground through vias (74).

Abstract: A transistor (42) is provided having a gate conductor (44) formed adjacent a semiconductor substrate (46) and separated therefrom by a gate insulator (48). Sidewall spacers (52, 54) are formed at the sides of gate conductor (44) and adjacent semiconductor substrate (46). Diffused regions (56, 58) are formed within semiconductor substrate (46) in order to provide source/drain regions for transistor (42). Positive charges from radiation are trapped within sidewall spacers (52, 54) thereby attracting negative charges from semiconductor substrate (46) such that a negative charge layer is created between diffused region (56) and gate edge (50a) and also between diffused region (58) and gate edge (50b).

Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

Abstract: A threshold control BiCMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.

Abstract: An extractor tool for removing a circuit module from a connector where the module has a substantial length, has a plurality of electrical contacts resiliently engaged with corresponding connector contacts, and has latch means at opposite ends receiving engagement by separate connector latches for detachably retaining the module on the connector. The tool has a thin flat body with spaced parallel legs extending from one side of the body to accommodate the substantial module length between the legs and has tapered surfaces on the edges of the distal ends of the legs to be pressed against the separate connector latches to release both of the latches at the same time to permit removal of the module from the connector free of damage to the latches or the resiliently engaged contacts.

Abstract: Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

Abstract: A circuit (90) converts a true ECL signal to a true TTL signal. The circuit includes a differential circuit (180) that receives an ECL signal having high and low values. The differential circuit produces a differential signal therefrom that has a high value in response to one of the high and low values of the true ECL signal, and a low value in response to the other of the high and low values of the true ECL signal. A first translator circuit (36, 64) has an input (32) coupled to the differential circuit (180). The first translator circuit (36, 64) transmits a true low TTL output (56) signal having a voltage level referenced to the voltage level of a TTL low supply voltage in response to receiving a high value of the differential signal. A second translator circuit (46, 52) has an input (38) and is coupled to a TTL high supply voltage and the output (56).

Abstract: A bias current supply circuit (20) is provided which includes an initial current source comprising a FET (22) coupled to a current mirror circuit comprising a pair of BJTs (26 and 28). An active resistive element comprising a second FET (24) is included to stabilize an output current I.sub.0 with respect to ambient temperature variations and process variations.

Abstract: A method for either block- or bit-erasing is described for an array of EEPROM cells, each having transistor channel regions with subchannels thereof respectively controlled by a floating gate conductor and a control gate. Erasing occurs through a Fowler-Nordheim tunnel window (34) between a source bit line (24) and a floating gate conductor (42) of a selected cell. For one or more selected cells, first and second erasing voltages are selected such that the selected source bit line (24) is more positive than the selected word line (48) by a voltage sufficient to cause excess electrons on the floating gate conductor (42) to be drawn through the tunnel window (34) to the source region (24). The nonselected word lines (48) have a nonerasing voltage impressed thereon that is sufficiently close to that of selected source regions that no erase disturb will occur in nonselected cells.

Abstract: A bipolar transistor and method of making the same is disclosed. The transistor has an emitter region which is diffused from polysilicon into the intrinsic base region, where the polysilicon is doped with two dopant species of different diffusivity. The impurity concentration of the higher diffusivity species, for example phosphorous, can be selected to define the emitter junction depth, which is preferably shallow, while the impurity concentration of the lower diffusivity species, for example arsenic, can be selected to provide a high conductivity emitter electrode, as well as reduce the sensitivity of the emitter electrode to counterdoping from the implantation of the extrinsic base region. The structure is compatible with BiCMOS processing, as the same anneal can be used to diffuse the emitter and the source/drains of the MOS transistors, with the emitter junction depth optimized via the implant conditions of the higher diffusivity species.

Abstract: A method and apparatus is disclosed for the non-destructive measurement of die-attach quality in packaged integrated circuit. The apparatus is used in a production line and uses acoustical pulses to generate signals from within the integrated circuit indicative of the die-attach quality.

Abstract: A mesa (31) is formed from polyimide (or a similar polymer material) to achieve a high thermal resistance. In an exemplary thermal imaging application, an array of thermal isolation mesa structures (30) are disposed on an integrated circuit substrate (20) for electrically connecting and bonding a corresponding focal plane array (5) of thermal sensors (10). Each mesa structure (30) includes a polyimide mesa (31) over which is formed a metal conductor (32) that extends from the top of the mesa down a mesa sidewall to an adjacent IC contact pad (22). When the focal plane array (5) is bonded to the corresponding array of thermal isolation mesa structure (30), a thermally isolated, but electrically conductive path is provided between the sensor signal electrode (16) of the thermal sensor (10) and the corresponding contact pad (22) of the integrated circuit substrate (20).

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit lines resistivity for a given cell density.

Abstract: A 2-transistor cell (26) comprises buried diffused regions (34, 36 and 38) aligned substantially parallel. Floating gates (40) are aligned substantially perpendicular to the diffused regions (34, 36 and 38). A control gate (42) defines a first channel region between first and second diffused regions (34 and 36) to define a read transistor (30) and a second channel region between second and third diffused regions (36 and 38) to define a program transistor. The read transistor (30) and program transistor (32) may be individually optimized according to their respective functions. Further, tunnel windows (70) may be provided for Fowler-Nordheim tunneling.

Abstract: A memory cell is disclosed comprising cross-coupled inverters including gated diodes connected in the cross-coupling which increase the memory cell's resistance to single event upset. The layouts for constructing such a memory cell, which optimize READ and WRITE speeds, are also disclosed.

Abstract: A vacuum-tight wafer carrier, and a load lock suitable for use with this wafer carrier. The wafers are supported at each side by a slightly sloping shelf, so that minimal contact (line contact) is made between the wafer surface and the surface of the shelf. This reduces generation of particulates by abrasion of the surface of the wafer. The carrier also contains elastic elements to restrain the wafers from rattling around, which further reduces the internal generation of particulates. When the wafer carrier is placed into the load lock, its body is lowered from beneath its cover through an aperture into a lower chamber, where wafers are loaded and unloaded under vacuum; the carrier cover remains covering the aperture into the lower chamber, so that the wafers never see any surface which is directly exposed to atmosphere. A wafer transport arm mechanism permits interchange of wafers among one or more processing stations and one or more load locks of this type.

Abstract: A pressure responsive variable capacitive transducer is shown in which a flat flexible diaphragm having a capacitor plate disposed thereon is mounted overlying a recess in a substrate having a capacitor plate disposed on the surface of the recess so that the plates are spaced apart a selected distance determined by the depth of the recess. In one embodiment a glass seal is located between the diaphragm and the substrate inwardly of the outer perimeter of the disphragm while in a second embodiment a glass seal is located outwardly from the outer perimeter of the diaphragm. The substrate is formed with bores adapted to receive electrical connection pins. Electrically conductive traces extend from electrically conductive layers to wells formed in the substrate contiguous with the bores to provide a gradual transition for the traces and an electrically conductive epoxy is infilled to electrically connect the pins to the traces.

Abstract: A laser pattern inspection and/or writing system which writes or inspects a pattern on a target on a stage, by raster scanning the target pixels. Inspection can also be done by substage illumination with non-laser light. A database, organized into frames and strips, represents an ideal pattern as one or more polygons. Each polygon's data description is contained within a single data frame. The database is transformed into a turnpoint polygon representation, then a left and right vector representation, then an addressed pixel representation, then a bit-mapped representation of the entire target. Most of the transformations are carried out in parallel pipelines. Guardbands around polygon sides are used for error filtering during inspection. Guardbands are polygons, and frames containing only guardband information are sent down dedicated pipelines. Error filtering also is done at the time of pixel comparisons of ideal with real patterns, and subsequently during defect area consolidation.

Abstract: The disclosure relates to a hybrid circuit wherein two substrates, preferably, though not necessarily, of diverse materials, are aligned on and secured to a glass plate by layers of polymer which are selectively etchable as to each other. The portion of the topmost polymer layer which is between the substrates is removed and the space therebetween is filled with an electrically insulating material which adheres to the substrates to form a surface between the substrates which is coplanar with the circuit containing surfaces of the substrates. Interconnects are then formed on the electrically insulating surface which extend onto both of the substrates. The remaining polymer layers are removed and the hybrid circuit which has been formed is then placed on a support to provide rigidity and, if necessary, heat sinking properties.

Abstract: A humidity sensor composed of interdigitated electrodes and a material therebetween which is composed of perfluorosulfonic acid substituted poly (tetrafluoroethylene) copolymer wherein H+ sites have undergone ion exchange with at least one of NH4+ and Li+, Na+, Ag+ and Mg+.