Abstract: Preferred embodiments include encoders and encoding methods for encoding integers as sparse binary vectors as used in neural networks. The encoding is by position of nonzero components; such as for N component vectors, the integer n is represented by a sequence of n components equal to zero followed by a sequence of log.sub.2 N components equal to one and then a sequence of N-n-log.sub.2 N components equal to zero. Other preferred embodiments include permutations of vector components while retaining the same number of nonzero components and also with partitioning into more and less significant subvectors.

Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicated NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines having a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Bitline isolation is by P/N junction or by oxide-filled trench, permitting relatively small spacing between transistors. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The resulting structure is a dense cross-point array of programmable memory cells.

Abstract: A method of preparing a substrate such as a semiconductor chip or ceramic thin film having vias for soldering to a substrate requires that a first metal that is resistive to solder bonding be deposited on the backside of the semiconductor device. The deposited metal is removed from the surface of the semiconductor device, leaving the vias of the semiconductor device having the first metal deposited through them. This technique is useful in any requirement requiring a solder or brazing barrier. This is, a photolithographic process in conjunction with a refractory or nonsolderable metal deposit is used to achieve an alloy or solder barrier.

Abstract: A chopper, in an infrared imaging system, is used to scatter infrared radiation from a viewed scene. This scattered radiation is detected with an infrared detector and used to produce a reference signal, which represents the uniform average radiance of the scene. This reference signal may be substracted from a signal representing the unscattered radiation emitted by the scene, to produce a signal that represents only radiance differences and that is an optimal signal for amplification.

Abstract: A fuel injection system having an air supply and a fuel injection spray valve furnishing an air-fuel mixture to an internal combustion engine has a fuel heating device for heating the fuel just prior to spraying from the valve to enhance fuel-air mixing, the heater having a housing comprising a pair of stiffly compressible housing elements clamped in sealing relation to each other for capturing a flat ceramic heating device of positive temperature coefficient of resistivity between the compressible housing elements, the elements each having a central opening and a spiral groove therein cooperating to form a chamber holding the heating device and for guiding fuel through the grooves in heat-transfer relation to the disc along spiral paths extending along each flat side of the heating disc, the housing having terminals sealed therein for electrically engaging opposite sides of the heating disc.

Abstract: A method of preventing forward biasing of PN junctions in junction isolated semiconductor devices to prevent parasitic transistor action. A biasing element is connected to the substrate/isolation regions to switch the regions to a low potential. The method is particularly well suited for implementation in the new multi-epitaxial semiconductor processes and structures.

Abstract: A translucent hemispherical diffuser provides shadowless, uniform illumination of an object to be inspected or otherwise viewed. The optical medium of the translucent diffuser has a milk glass optical consistency, and/or one or more surfaces of the diffuser may be textured to diffuse light entering or leaving the optical medium of the diffuser. The hemispherical diffuser is placed between a light source and the object to be viewed. Light from the light source entering the optical medium of the diffuser is re-radiated uniformly from the concave surface of the diffuser. The object to be viewed is located approximately at the center of curvature of the hemispherical diffuser. Thus, the radiating concave surface of the diffuser subtends a solid angle of approximately two -pi steradians. Light may be scattered and diffused by various reflecting surfaces external to the diffuser, prior to entering the optical medium of the diffuser.

Abstract: A universal sensor has a selectivity scaled condition responsive element such as a capacitive pressure transducer mounted on a common support with signal conditioning means embodied in an integrated circuit to provide a control signal precisely corresponding to a sensed condition. Electrically actuatable means on the support are incorporated in the circuit for low cost, mass producible calibration of the circuit and condition-responsive element relative to each other after assembly on the common support. Preferably, a capacitive pressure transducer and a reference capacitor are arranged in a charge-locked loop relation with a common node while an array of switches cycles the voltage across the transducer and reference capacitors with opposite transitions with a predetermined frequency so change in transducer capacitance results in a differential voltage at the common node.

Abstract: An electrically-erasable, electrically-programmable ROM or an EEPROM is constructed using a floating-gate transistor with or without a split gate. The floating-gate transistor may have a self-aligned tunnel window of sublithographic dimension positioned on the opposite side of the source from the channel and drain, in a contact-free cell layout, enhancing the ease of manufacture and reducing cell size. In this cell, the bitlines and source/drain regions are buried beneath relatively thick silicon oxide and the floating gate extends over the thick silicon oxide. Programming and erasing are accomplished by causing electrons to tunnel through the oxide in the tunnel window. The tunnel window has a thinner dielectric than the remainder of the oxides under the floating gate to allow Fowler-Nordheim tunneling. Trenches and ditches are used for electrical isolation between individual memory cells, allowing an increase in cell density.

Abstract: A high limit thermostat for gas furnace applications is shown having a molded base plate and an elongated housing formed integrally with the base plate which mounts a thermostat at a free end of the housing in order to be positioned within an air stream of a heat exchanger to sense temperature conditions of the air stream.

Abstract: A dynamic read/write memory cell array employs stacked capacitors consisting of three levels of conductor separated by dielectric material. In one embodiment, the central level is a common plane, and the upper and lower levels are connected to the source regions of the pair of access transistors of two adjacent cells. In this manner, capacitors for adjacent cells occupy the same area, almost doubling the capacitor value per unit area.

Abstract: A sensor system (50) for measurements of semiconductor wafer minority carrier lifetime. The sensor (50) includes a microwave source (78) for generating a plurality of microwave signals and a waveguide (52) for emitting the microwave signals in the direction of the semiconductor wafer (20) in a processsing chamber (18). A collector waveguide (84) detects the reflected microwave signals from the semiconductor wafer (20) and directs the microwave signals to and from the emitter waveguide (52) so as to generate a plurality of electrical signals relating to semiconductor wafer (20) physical properties. A photon energy source (102) intermittently emits photon energy in the direction of the semiconductor wafer (20). Based on the differing microwave reflectance measurements following the injection and removal of photon energy, process control computer (76) calculates semiconductor substrate physical characteristics.

Abstract: A circuit breaker has two thin flat terminals embedded in an electrically insulating housing exposing respective broad flat sides of the terminals in spaced side-by-side relation to each other in a housing chamber. The circuit breaker has a thermostat metal member secured at one end to one exposed side of one terminal to mount the member extending along a chamber wall and has a contact at its opposite end to engage and disengage the other terminal to close and open a circuit in response to a selected current in the circuit. The contact comprises a material which erodes during repeated cycling of the circuit breaker. The thermostat metal member has a portion of reduced cross-sectional area adapted to burn out and separate the member into two sections to open the circuit if the contact welds or sticks to the other terminal. A stop on the housing intercepts movement of one of the member sections after burn out to avoid shorting of the circuit.

Abstract: A method is provided for forming multiple layers of interconnection adjacent a planar surface. A first insulator layer is formed adjacent the selected planar surface. A first conductor layer is formed adjacent the first insulator layer. A second insulator is formed adjacent the first conductor layer. A first cavity and a second cavity are formed, each having sidewalls extending through said second insulator layer and said first conductor layer. The first cavity is formed wider than the second cavity. A third insulator layer is conformally deposited adjacent the second insulator layer, such that sidewall insulators are deposited on sidewalls of the first cavity and such that the second cavity is substantially filled with insulator. An etch is performed through the first cavity to expose a portion of the planar surface. A second conductor layer is conformally deposited adjacent third insulator layer such that second conductor layer extends through the first cavity to contact the planar surface.

Abstract: The invention provides a bipolar transistor structure on a buried oxide layer for use in an integrated circuit and a method for fabricating the same. The invention may be incorporated into a method for fabricating bipolar transistors in a BiCMOS structure. The bipolar transistor is constructed in two stacked epitaxial layers. The first epitaxial layer is used to form both the MOSFET and the buried collector of the bipolar transistor. The second epitaxial layer is grown as a blanket epitaxial layer. The intrinsic collector and the base of the bipolar transistor are formed in the second epitaxial layer. An oxide layer is formed over the base. The emitter is formed of a polysilicon layer which is deposited through an opening in the oxide layer such that the polysilicon layer contacts the second epitaxial layer.

Abstract: An internal combustion engine of the injector type has self-regulating electrical resistance heating devices of positive temperature coefficient of resistivity arranged in cylinder head air-fuel inlet channels to intercept fuel directed into the channels by fuel injectors for heating and deflecting the fuel into respective cylinder intake valve openings. The heating devices and/or fuel injectors are movable after engine warm-up so that the fuel injectors thereafter spray fuel directly onto warmed-up intake valves in the valve openings without being intercepted by the heaters, whereby the heaters are adapted to be deenergized after engine warm-up without creating a cold spot in the engine fuel supply system at the heater location.

Abstract: A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolate N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

Abstract: A novel composite metal material comprises a ferrous metal of relatively low thermal expansion properties and a silver metal substantially free of ferrous constituents having a relatively high thermal conductivity which cooperate in a novel way to provide the composite material with an effective thermal expansion coefficient corresponding to that of various silicon or gallium arsenide semiconductor devices and the like for reliably mounting the devices while also providing paths of high conductivity silver metal extending through the composite material to provide improved heat-dissipation from the semiconductor devices. A circuit system mounts a semiconductor device using the novel composite metal material alone, bonded to other support materials, or formed into a selected shape. In one preferred embodiment, the composite material is used in a novel heat-dissipating member having components of different shape which are bonded together.

Abstract: A normally closed pressure responsive switch has upper and lower housings attached to one another with an electrically conductive snap acting disc placed therebetween. The lower housing includes a base having a recessed area in which a stationary electrical contact is mounted. The snap acting disc is placed on top of the base with a side having a convex configuration facing the stationary contact. An electrically conductive member is placed over the disc with a plurality of contact tabs engageable with the outer peripheral portion of the disc. The upper housing includes a retainer having a bore in which a pressure converter slides. Ribs formed on the bottom of the pressure converter are adapted to engage the outer peripheral portions of the disc between the contact tabs and are captured in grooves of the retainer to restrict angular movement of the pressure converter.

Abstract: A semiconductor dynamic read/write memory device contains an array of rows and columns of one-transistor memory cells with a different sense amplifier for each column of cells. The sense amplifier has a pair of balanced bit lines extending from its inputs, in a folded bit line configuration. The memory cells are not directly connected to the bit lines, but instead are coupled to bit line segments. The row address selects a cell to be connected to a segment, and also selects a segment to be connected to the bit line. The ratio of storage capacitance to effective bit line capacitance is increased, because the bit line itself is of lower capacitance to the substrate.