Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATH1-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Abstract: Electrical terminal pins (start, main and common) mounted in a glass header to provide electrical connection to a compressor motor are shown with a motor protector disposed on one of the pins in such a fashion that opposite-direction-oriented right angle female flag quick connectors are required for the start and main terminals, thereby avoiding the possibility of miswiring the terminal pins. The opening temperature of the motor protector is adjustable and the protector has a fail safe mechanism to avoid subjecting the motor to overtemperature conditions.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously. This architecture allows propagation delays between devices to be determined. A driving device (264) toggles its input on a first clock edge. On a subsequent clock edge, the receiving circuit (266) samples its input.

Abstract: A Zener diode structure comprising a semiconductor substrate layer of a first conductivity type, a first epitaxially formed semiconductor layer of the first conductivity type disposed on the substrate layer, a second epitaxially formed semiconductor layer of a second conductivity type disposed on the first semiconductor layer, a third semiconductor layer of the first conductivity type disposed over the second semiconductor layer, a buried layer of the first conductivity type disposed between and contacting the second and third semiconductor layers and a semiconductor contact region of the second conductivity type extending between and contacting a surface of the third semiconductor layer and the buried layer, the semiconductor contact region being an anode of a Zener diode, the buried layer being a cathode of the Zener diode.

Abstract: In an improved selection tungsten metallization system, a plurality of orifices (20) are cut into a first level dielectric layer (18). A nucleation layer (52), preferably Ti-W alloy, is then formed in each orifice (20) and on the outer surface of the first dielectric layer (18) in a second-level metallization pattern. A second dielectric layer (30) is deposited over the first dielectric layer (18) and the nucleation layer (52), and a reverse second level metallization pattern is used to etch slots (58) back down to the nucleation layers (52) and into orifices (20). Thereafter, tungsten is deposited by selective CVD to fill the first level orifices (20) and the second level slots (58) until the upper surfaces (62) of the tungsten conductors (60) are substantially coplanar with the upper surface (38) of the second dielectric layer (30).

Abstract: A sense amplifier including a pair of P-conductivity-type current-mirror transistors, a N-conductivity-type reference transistor and a cascode-connected N-conductivity-type transistor and inverter connected according to prior-art. The amplifier also includes a N-conductivity-type pre-charge transistor with source-drain path connected in parallel with the source-drain path of P-conductivity-type mirror load transistor. The gate of the pre-charge transistor is connected to the gate of the N-conductivity-type cascode transistor, which is also connected to the output of cascode inverter.The pre-charge transistor functions to bypass the mirror load transistor when a discharged bitline is selected. As a result, the current charging the bitline capacitance is increased and the time needed for charging is decreased.

Abstract: A substrate is provided for mounting semiconductor devices and comprises an electrically conductive circuit layer, a base layer of an aluminum metal material, and an electrically insulating hard coating dielectric layer of amorphous aluminum oxide which is directly adherent to the base layer for mounting the electrically conductive circuit layer thereon.

Abstract: The disclosure relates to a semiconductor circuit on a single chip, preferably of gallium arsenide, wherein insulating layers with vias therein for receiving metallization include a thin silicon nitride layer beneath a relatively much thicker silicon oxide layer with the nitride exposed on the via side walls to contact gold in the metallization within the via. The disclosure further includes metallization formed as a TiW/Au/TiW sandwich wherein the TiW layer contacting the insulator on the substrate is formed of a first tensile film of TiW with a compressive film of TiW of substantially the same thickness thereover and in contact therewith to lower the tensile force applied by the tensile layer, yet maintain the resultant force tensile.

Abstract: A graphics processor device is disclosed which performs bit-by-bit masking outside of the central processing unit, by way of a read-modify-write cycle to external or internal memory. A mask bus is incorporated into the device so that, for each bit of the external data word, a mask bit is present which indicates whether data from the central processing unit (CPU) is to be written to memory (unmasked) or if that bit of memory contents is to remain unaltered (masked). The CPU data is written into a latch at the memory interface during such time as the latch is isolated from the external memory bus and during the read portion of the read-modify-write cycle. For those bits which are to be masked, the latch is overwritten with the data read from memory, while for the unmasked bits the latch remains isolated from the external memory bus. During the write portion of the read-modify-write cycle, the contents of the latch are driven onto the external memory bus.

Abstract: Data selector circuit including a plurality of data registers connected in parallel via corresponding output buffers to a plurality of output drivers, wherein a decoder and selector portion is interposed between the output buffers and the output drivers for selectively providing one of a plurality of serial data output sequences from the data registers to the output drivers rather than a parallel data output format from the plurality of data registers which would otherwise occur. The decoder and selector portion is controlled by a partial address buffer which is provided with serial sequence selection data.

Abstract: A communication receiver (12) is provided having a radio frequency section (20) for receiving a communication signal (14) and a corresponding code signal (16) carrying an identification code. An intermediate frequency section (26) is coupled to radio frequency section (20) to convert the frequency of said communication signal. A decoder (42) having a memory for storing a security code, is coupled to radio frequency section (20) and intermediate frequency section (26). Decoder (20) is operable to compare the identification code and the security code and selectively disable the intermediate frequency section in response.

Abstract: A transponder arrangement is described comprising an interrogation unit (10) which sends an RF interrogation pulse to at least one responder unit (12). The responder unit (12) then transmits back data stored therein in the form of a modulated RF carrier to the interrogation unit (10). In the responder unit (12) is an energy accumulator (136) which stores the energy contained in the RF interrogation pulse. The responder unit (12) further contains means (142, 148) which in dependence upon the termination of the reception of the RF interrogation pulse and the presence of a predetermined energy amount in the energy accumulator (126) initiate the excitation of an RF carrier wave generator (130, 132, 134) operating with the frequency contained in the RF interrogation pulse.

Abstract: A device having a circled array of tapered motor driven rollers center and find the flat edge of a semiconductor wafer by rotating the wafer until the flat edge is over a photo cell, at which time finder rollers secure the wafer in its centered and orientated position.

Abstract: A method for preventing single event upsets (SEUs) in MOS circuits is disclosed. A resistive area (88, 89) is situated in a semiconductor device such that when a high energy particle passes through the device and the resistive area (88, 89) the stray carriers caused by the particle will pass through the resistive area (88, 89) causing a voltage drop which will prevent the upset of the MOS circuit. A low resistance path is provided for the normal operating current in the device so that the normal operating parameters of the device are not affected by the protection provided by the resistive area (88, 89).

Abstract: A motor winding system having a main winding and a start winding circuit with a start winding and a PTC resistor in series therewith wherein the resistor is electrically removed from the circuit at a predetermined time after motor starting and remains in this state until motor shut off. The start winding circuit also includes a bimetallic switch in series with the resistor and a series circuit of a capacitor and an electromagnet in parallel with the resistor and switch. At motor start up, current from the main power source is applied across the main winding and the start winding circuit heats up the resistor and causes an increase in the resistance thereof. Also, current through the switch and PTC heat causes the bimetallic element to snap or move when it has reached a predetermined temperature to open the start winding circuit.

Abstract: One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

Abstract: A scanning electron microscope (SEM) (24), or other irradiating device, is used to create a potential in sample areas (39b) of a test structure (39) formed on the surface of an integrated circuit wafer. A conduction path between the irradiated sample area and a common area (39a) is detected via an ammeter (40) connected between the sample area (39b) and a voltage source (42). Monitoring circuit (44) produces an output indicative of those sample areas (39b) which are electrically coupled to the common area (39a).

Abstract: Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced.

Abstract: A system scan path architecture is provided by a device select module (DSM) (18) which may be used in conjunction with associated circuits (16a-b) to select secondary scan paths (PATHl-m) on each circuit for coupling with a primary scan path on a test bus (14). The test bus (14) is controlled by a primary bus master (12). Remote bus masters (124) may be used in conjunction with the DSMs (18) to provide serial-scan testing independent of the primary bus master (12).

Abstract: A speaker verification system receives input speech from a speaker of unknown identity. The speech undergoes linear predictive coding (LPC) analysis and transformation to maximize separability between true speakers and impostors when compared to reference speech parameters which have been similarly transformed. The transformation incorporated a "inter-class" covariance matrix of successful impostors within a database.