Patents Represented by Attorney Mikio Ishimaru

Find this attorney in the Justia Lawyer Directory

  • Integrated circuit packaging system with layered packaging and method of manufacture thereof
    Patent number: 7863100
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a base package having a base interposer; forming an intermediate package having an intermediate interposer and an intermediate package embedded link trace, the intermediate package embedded link trace being encapsulated in an intermediate package mold compound; forming a cap package having a cap interposer; and connecting the intermediate package to the cap package and the base package using the intermediate package embedded link trace.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Joungln Yang, Dongjin Jung, DongSam Park
  • Integrated circuit packaging system with a tiered substrate package and method of manufacture thereof
    Patent number: 7863735
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; applying a tiered encapsulant above the base substrate, the tiered encapsulant having a first cavity above the base substrate and a second cavity above the first cavity adjacent an intermediate horizontal side; connecting an intermediate interconnect to the base substrate, the intermediate interconnect surrounded by the tiered encapsulant and substantially exposed on the intermediate horizontal side; and connecting a top interconnect to the base substrate, the top interconnect surrounded by the tiered encapsulant and substantially exposed on a top horizontal side.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: NamJu Cho, HeeJo Chi, HanGil Shin
  • Array-molded package heat spreader and fabrication method therefor
    Patent number: 7863730
    Abstract: A method for forming a heat spreader, and the heat spreader formed thereby, are disclosed. An array heat spreader having a plurality of connected heat spreader panels is formed. Slots are formed in opposing sides of the heat spreader panels. Legs are formed on and extending downwardly from each of the heat spreader panels in at least an opposing pair of the slots on the heat spreader panels. The legs are integral with the respective heat spreader panels from which they depend.
    Type: Grant
    Filed: August 18, 2004
    Date of Patent: January 4, 2011
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Il Kwon Shim, Kambhampati Ramakrishna, Diane Sahakian, Seng Guan Chow, Dario S. Filoteo, Jr., Virgil Cotoco Ararao
  • Ball grid array package system
    Patent number: 7863732
    Abstract: A ball grid array package system comprising: forming a package base including: fabricating a heat spreader having an access port, attaching an integrated circuit die to the heat spreader, mounting a substrate around the integrated circuit die, and coupling an electrical interconnect between the integrated circuit die and the substrate; and coupling a second integrated circuit package to the substrate through the access port.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Lionel Chien Hui Tay
  • Circuit system with circuit element
    Patent number: 7863706
    Abstract: A circuit system includes: forming a first electrode over a substrate; applying a dielectric layer over the first electrode and the substrate; forming a second electrode over the dielectric layer; and forming a dielectric structure from the dielectric layer with the dielectric structure within a first horizontal boundary of the first electrode.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Yaojian Lin
  • Integrated circuit package system with package substrate having corner contacts and method of manufacture thereof
    Patent number: 7863726
    Abstract: A method of manufacture of an integrated circuit package system includes: forming a package substrate with a top substrate side and a bottom substrate side; forming a corner contact in a first corner of the bottom substrate side, the corner contact extending to a substrate edge of the package substrate; mounting an integrated circuit device over the top substrate side; connecting an electrical interconnect between the integrated circuit device and the top substrate side; and forming a package encapsulation over the top substrate side, the integrated circuit device, and the electrical interconnect.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Tae Hoan Jang
  • Integrated circuit package system with overhanging connection stack
    Patent number: 7863099
    Abstract: An integrated circuit package system comprising: providing a first conductive line adjacent to a second conductive line; forming a first connection stack over the first conductive line with the first connection stack overhanging the second conductive line; connecting an integrated circuit device and the first connection stack; and encapsulating the integrated circuit device and the first connection stack.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Seng Guan Chow
  • Integrated circuit package system with external interconnects within a die platform
    Patent number: 7863102
    Abstract: The present invention provides an integrated circuit package system comprising: attaching a die platform to an integrated circuit die; mounting the integrated circuit die over an external interconnect with a bottom side of the external interconnect partially within the die platform; connecting the integrated circuit die and the external interconnect; and forming an encapsulation over the integrated circuit die with the external interconnect partially exposed.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: January 4, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Lionel Chien Hui Tay, Seng Guan Chow
  • Integrated circuit package system for stackable devices
    Patent number: 7859094
    Abstract: An integrated circuit package system provides: forming a stack module including: providing a stack die and encapsulating the stack die with an insulating material having a protruding support and a pad connected to the stack die; mounting the stack module on a package base; connecting the pad to the package base; mounting a top die on the protruding support; connecting the top die to the package base; and encapsulating the top die, the package base, and the stack module with a package encapsulant.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Rui Huang, Heap Hoe Kuan
  • Package system incorporating a flip-chip assembly
    Patent number: 7859120
    Abstract: A package system including providing a first semiconductor die; mounting a second semiconductor die on the first semiconductor die using an inter-die interconnect to form a flip-chip assembly; and attaching the flip-chip assembly on a package substrate with a contact pad, a test connection, a z-bond pad, and a die receptacle, with the first semiconductor die in the flip-chip assembly fitting inside the die receptacle.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Young Jin Woo, Junwoo Myung
  • Embedded integrated circuit package system
    Patent number: 7859098
    Abstract: An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: You Yang Ong, Dioscoro A. Merilo, Seng Guan Chow
  • Voltage regulation system
    Patent number: 7859236
    Abstract: A voltage regulation system is provided including detecting a feedback voltage less than a reference voltage; asserting a current source gate output by the feedback voltage less than the reference voltage; activating a gated current source by the current source gate output; and waiting a delay interval before negating the current source gate output for turning off the gated current source.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: December 28, 2010
    Assignee: Micrel, Inc.
    Inventors: Matthew Weng, Charles Vinn, Raymond David Zinn
  • Integrated circuit packaging system having through silicon via with direct interconnects and method of manufacture thereof
    Patent number: 7859099
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a through silicon via die having an interconnect through a silicon substrate; depositing a re-distribution layer on the through silicon via die and connected to the interconnects; mounting a structure over the through silicon via die; connecting the structure to the interconnect of the through silicon via die with a direct interconnect; and encapsulating the through silicon via die and partially encapsulating the structure with an encapsulation.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: December 28, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: A Leam Choi, Jae Han Chung, DeokKyung Yang, HyungSang Park
  • Integrated circuit package system with an encapsulant cavity and method of fabrication thereof
    Patent number: 7855100
    Abstract: An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: December 21, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Byung Joon Han, Kambhampati Ramakrishna, Seng Guan Chow
  • Mountable integrated circuit package system with substrate
    Patent number: 7855444
    Abstract: A mountable integrated circuit package system includes: providing a substrate having an opening provided therein; providing an encapsulated integrated circuit package having an external leadfinger; mounting the encapsulated integrated circuit package by the external leadfinger proximate to the opening in the substrate; and connecting the external leadfinger and the substrate.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: December 21, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Albelardo Jr. Hadap Advincula, Henry Descalzo Bathan, Lionel Chien Hui Tay
  • Integrated circuit stacking system with integrated passive components
    Patent number: 7851257
    Abstract: An integrated circuit stacking system is provided including fabricating an integrated passive device including: providing a semiconductor substrate, forming an integrated inductor, a resistor block, or an integrated capacitor integrated on the semiconductor substrate, and forming contact pads, on the semiconductor substrate, coupled to the integrated inductor, the resistor block, or the integrated capacitor; positioning an integrated circuit die for maintaining an inductor spacing; mounting the integrated circuit die on the integrated passive device; and encapsulating the integrated circuit die and the integrated passive device.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: December 14, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Pandi Chelvam Marimuthu, Robert Charles Frye, Yaojian Lin
  • Electronic system with removable computing device and mutable functions
    Patent number: 7853745
    Abstract: An electronic system is provided including providing a receptacle, inserting a removable computing device into the receptacle, adjusting based on the removable computing device, and operating a feature based on the removable computing device.
    Type: Grant
    Filed: February 23, 2007
    Date of Patent: December 14, 2010
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Yosuke Muraki
  • Integrated circuit package system using heat slug
    Patent number: 7851268
    Abstract: An integrated circuit package system includes providing a substrate having an integrated circuit die thereon. A support is provided on the substrate. A heat slug having a tie bar is positioned by the tie bar on the support. The substrate and the integrated circuit die are encapsulated with an encapsulant, the encapsulant in contact with the heat slug. The substrate, heat slug, and encapsulant are singulated to remove the support.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: December 14, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Kyungsic Yu, Tae Keun Lee, Youngnam Choi
  • Signal processing system and method of operation for nonlinear signal processing
    Patent number: 7852380
    Abstract: A signal processing system includes: defining a nonlinear function; defining a set of requirements for an output signal; obtaining an input signal; applying a cubic polynomial fitting to approximate the nonlinear function and provide an approximated nonlinear function; assigning a set of fitted polynomial parameters to the approximated nonlinear function; transforming the input signal with the approximated nonlinear function to provide a transformed signal; modifying the transformed signal by adjusting the set of fitted polynomial parameters to provide a modified signal meeting the set of requirements for the output signal; and outputting the modified signal.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 14, 2010
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Xiaoling Wang, Alexander Berestov, Takami Mizukura, Naoya Katoh
  • Integrated circuit packaging system with package stacking and method of manufacture thereof
    Patent number: 7847382
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an encapsulation surrounding an integrated circuit having an inactive side and an active side exposed; forming a hole through the encapsulation with the hole not exposing the integrated circuit; forming a through conductor in the hole; and mounting a substrate with the integrated circuit surrounded by the encapsulation with the active side facing the substrate.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 7, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do