Abstract: An integrated circuit package system includes an integrated circuit die, a first controlled bump over the integrated circuit die, a second controlled bump over the integrated circuit die, and a connector between the first controlled bump and the second controlled bump.
Abstract: A mountable integrated circuit package system includes: providing a base; depositing a photoresist on the base; patterning the photoresist with an opening; filling the opening with a metal; depositing a further metal on the metal to form a lead pad; removing the photoresist; attaching a die over the base; bonding wires between the die and the lead pad; encapsulating the die and the lead pad in an encapsulation formed into a lead pad lock adjacent the lead pad; and removing the base.
Type:
Grant
Filed:
December 26, 2007
Date of Patent:
May 24, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua
Abstract: A thin package system with external terminals and a leadframe is provided. An external bond finger defining template is provided and used to form external bond fingers on the leadframe. A die is provided and attached to the leadframe. At least portions of the die and the external bond fingers are encapsulated, and the leadframe is removed.
Type:
Grant
Filed:
October 22, 2005
Date of Patent:
May 24, 2011
Assignee:
STATS ChipPAC Ltd.
Inventors:
Youngcheol Kim, Myung Kil Lee, Gwang Kim, Koo Hong Lee
Abstract: An integrated circuit package system is provided including: forming a plurality of leads with a predetermined thickness and a predetermined interval gap between each of the plurality of leads; configuring each one of the plurality of leads to include first terminal ends disposed adjacent an integrated circuit and second terminal ends disposed along a periphery of a package; and forming the second terminal ends of alternating leads disposed along the periphery of the package to form an etched lead-to-lead gap in excess of the predetermined interval gap.
Type:
Grant
Filed:
February 4, 2006
Date of Patent:
May 24, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Keng Kiat Lau
Abstract: A wafer level chip scale package system is provided forming a wafer having an interconnect provided on an active side, forming a thermal sheet having a first thermal interface material layer and a thermal conductive layer, and attaching the thermal sheet on a non-active side of the wafer.
Type:
Grant
Filed:
March 7, 2006
Date of Patent:
May 10, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Seng Guan Chow, Byung Tai Do, Heap Hoe Kuan
Abstract: An integrated circuit package system includes forming lead structures including a dummy tie bar having an intersection with an outer edge of the integrated circuit package system, and connecting an integrated circuit die to the lead structures.
Type:
Grant
Filed:
November 9, 2006
Date of Patent:
May 3, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Zigmund Ramirez Camacho
Abstract: An integrated circuit package system is provided including forming a first external interconnect and a die paddle having a slot, forming an inner terminal from a peripheral region of the die paddle, connecting an integrated circuit die and the peripheral region for ground connection, and molding through the slot.
Type:
Grant
Filed:
August 23, 2006
Date of Patent:
May 3, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Antonio B. Dimaano, Jr., Pandi Chelvam Marimuthu
Abstract: An integrated circuit package system includes: providing a die attach paddle with interconnection pads connected to a bottom surface of the die attach paddle; connecting a first device to the interconnection pads with a bond wire; connecting a lead to the interconnection pad or to the first device; encapsulating the first device and the die attach paddle with an encapsulation having a top surface; and etching the die attach paddle leaving a recess in the top surface of the encapsulation.
Abstract: A method for fabricating a multichip module package includes providing a first heat sink positioned for releasing heat from the package and providing a second heat sink positioned proximate the first heat sink. The heat sinks are thermally coupled and electrically isolated to and from one another. A first semiconductor device is attached to the first heat sink in thermal and electrical communication therewith and electrically insulated from the second heat sink. A second semiconductor device is attached to the second heat sink in thermal and electrical communication therewith and electrically insulated from the first heat sink.
Type:
Grant
Filed:
September 24, 2008
Date of Patent:
April 19, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Il Kwon Shim, Dario S. Filoteo, Jr., Tsz Yin Ho, Sebastian T. M. Soon
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base circuit assembly having an integrated circuit device; mounting a pre-formed conductive frame having an outer interconnect and an inner interconnect shorter than the outer interconnect over the base circuit assembly, the inner interconnect over the integrated circuit device and the outer interconnect around the integrated circuit device; applying an encapsulant over the inner interconnect and the outer interconnect; and removing a portion of the pre-formed conductive frame exposing an end of the inner interconnect and an end of the outer interconnect.
Type:
Grant
Filed:
June 19, 2009
Date of Patent:
April 19, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Reza Argenty Pagaila, Byung Tai Do, Jong-Woo Ha
Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.
Type:
Grant
Filed:
November 10, 2006
Date of Patent:
April 19, 2011
Assignee:
STATS ChipPAC Ltd.
Inventors:
Il Kwon Shim, Antonio B. Dimaano, Jr., Henry D. Bathan, Jeffrey D. Punzalan
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a carrier having a planar surface and a cavity therein, a first barrier between the planar surface and a first interconnect, and a second barrier between the cavity and a second interconnect; providing a substrate; mounting an integrated circuit over the substrate; mounting the carrier to the substrate with the first interconnect and the second interconnect attached to the substrate and with the planar surface over the integrated circuit; forming an encapsulation between the substrate and the carrier covering the integrated circuit, the encapsulation having an encapsulation recess under the planar surface and over the integrated circuit; and removing a portion of the carrier to expose the encapsulation, a portion of the first barrier to form a first contact pad, and a portion of the second barrier to form a second contact pad.
Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.
Type:
Grant
Filed:
March 27, 2009
Date of Patent:
April 12, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Chan Hoon Ko, Soo-San Park, YoungChul Kim
Abstract: An integrated circuit package system includes: a substrate; a first device attached to the substrate; a shield attached to the substrate and surrounding the first device; apertures formed within the shield; the shield configured to block electromagnetic energy that passes through the apertures; and an encapsulation material deposited through the apertures.
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside the conductive pillar; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond.
Abstract: A multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die.
Type:
Grant
Filed:
May 15, 2008
Date of Patent:
April 12, 2011
Assignee:
STATS ChipPAC Ltd.
Inventors:
Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan, Linda Pei Ee Chua, Rui Huang
Abstract: An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a substrate that includes the integrated circuit system; providing a second mask including a second feature; aligning the second mask over the image of the first mask to form an overlap region; and exposing the second mask to the radiation source to form an image of the second feature on the photoresist material that is larger than the structure to be formed.
Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead to include a first tip at one end, a second tip on the end opposite from the first tip with a connect area between each end located above the first tip, and a first tier section or a second tier section located between the connect area and the second tip; connecting a bottom component assembly to the first tier section or the second tier section; connecting a top component assembly over the connect area; and applying an encapsulant over and under the connect area with the first tip exposed.
Type:
Grant
Filed:
September 18, 2009
Date of Patent:
April 5, 2011
Assignee:
Stats Chippac Ltd.
Inventors:
Zigmund Ramirez Camacho, Jose Alvin Caparas, Arnel Senosa Trasporto
Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead; mounting an inner package so that the lead is peripheral to the inner package, and the inner package having a connection pad; forming an exposed terminal interconnect on the connection pad; and encapsulating the inner package, and partially encapsulating the exposed terminal interconnect with an encapsulation.
Abstract: A method of manufacture of an integrated circuit package system includes forming a paddle having a paddle top surface, the paddle top surface having a depression provided therein, forming an external interconnect having a lead tip and a lead body with the lead body having a first recess segment along a length-wise dimension of the lead body, connecting a device over the paddle top surface and the external interconnect, and filling a substantially electrically nonconductive material in the depression.