Patents Represented by Attorney Mikio Ishimaru

Find this attorney in the Justia Lawyer Directory

  • Integrated circuit package system with dual side connection
    Patent number: 7884457
    Abstract: An integrated circuit package system comprising: connecting an integrated circuit die with a bottom connection structure; placing an adhesive encapsulation over the integrated circuit die and the bottom connection structure with the bottom connection structure exposed; and placing a top connection structure over the adhesive encapsulation at an opposing side to the bottom connection structure.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: February 8, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, SeungYun Ahn, JoHyun Bae
  • Integrated circuit with step molded inner stacking module package in package system
    Patent number: 7875967
    Abstract: An integrated circuit package system including: providing a substrate; mounting an integrated circuit above the substrate; mounting an inner stacking module, having an inner stacking module encapsulation and a molded integral step molded in the inner stacking module encapsulation, above the integrated circuit; and encapsulating the inner stacking module, and the integrated circuit with an encapsulation.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: January 25, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DeokKyung Yang, In Sang Yoon, Jae Han Chung
  • Stacked integrated circuit and package system
    Patent number: 7875966
    Abstract: A stacked integrated circuit and package system including attaching a first top integrated circuit over an upper surface of a top substrate, attaching a second top integrated circuit over a lower surface of the top substrate, forming top electrical connectors on the lower surface of the top substrate, and connecting a bottom package to the top electrical connectors.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: January 25, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Tae Sung Jeong, Hyeog Chan Kwon, Youngcheol Kim
  • Integrated circuit package system with multiple molding
    Patent number: 7871863
    Abstract: An integrated circuit package system is provided forming a lead from a padless lead frame, and encapsulating the lead for supporting an integrated circuit die with a first molding compound for encapsulation with a second molding compound.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: January 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jose Alvin Caparas, Arnel Senosa Trasporto, Jeffrey D. Punzalan
  • Integrated circuit package system employing an offset stacked configuration
    Patent number: 7872340
    Abstract: A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically coupled to the base substrate via a system interconnect.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: January 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, BumJoon Hong, Sang-Ho Lee, Jong-Woo Ha, Soo-San Park
  • Stacked integrated circuit package system with intra-stack encapsulation
    Patent number: 7871861
    Abstract: A stacked integrated circuit package system includes: mounting a first integrated circuit over a first carrier; mounting a second integrated circuit package system having a second carrier with an intra-stack interconnect attached thereto and with the intra-stack interconnect over the first carrier and the first integrated circuit; and forming an intra-stack encapsulation between the first carrier and the second carrier surrounding the intra-stack interconnect.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: January 18, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Sungmin Song, Junwoo Myung, Byoung Wook Jang
  • Ball grid array package stacking system
    Patent number: 7871862
    Abstract: A ball grid array package stacking system includes: forming a heat spreader having a centrally located access port; mounting a substrate in the heat spreader for providing a connection pad in the centrally located access port; coupling an integrated circuit die to the substrate; and coupling a system interconnect to the integrated circuit die, the connection pad, or a combination thereof.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: January 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Lionel Chien Hui Tay
  • Integrated circuit package system with rigid locking lead
    Patent number: 7872345
    Abstract: An integrated circuit package system includes: providing a protective layer having an opening; forming a conductive layer over the protective layer and filling the opening; patterning a rigid locking lead, having both a lead locking portion and a lead exposed portion, from the conductive layer; connecting an integrated circuit and the rigid locking lead; and forming an encapsulation over the integrated circuit with the lead locking portion in the encapsulation and the lead exposed portion exposed from the encapsulation.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: January 18, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Linda Pei Ee Chua, Heap Hoe Kuan
  • Reticle system for manufacturing integrated circuit systems
    Patent number: 7867698
    Abstract: A reticle system that includes: providing a reticle system; and assigning two or more of an image pattern onto the reticle system to form one or more layers of an integrated circuit system by grouping and pairing each of the image pattern onto the reticle system according to a multi-layer reticle grouping/pairing flow.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: January 11, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Gek Soon Chua, Sia Kim Tan, Byoung-IL Choi, Ryan Chong, Martin Yeo
  • Integrated circuit package-in-package system with leads
    Patent number: 7868471
    Abstract: An integrated circuit package-in-package system includes: forming an integrated circuit package system including: connecting a first integrated circuit die and a lead, and forming an inner encapsulation covering the first integrated circuit die and a portion of the lead; mounting a second integrated circuit die to the integrated circuit package system; connecting the second integrated circuit die and the lead; and forming a package encapsulation covering the integrated circuit package system and the second integrated circuit die with the lead exposed.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: January 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Trasporto, Jeffrey D. Punzalan, Abelardo Hadap Advincula, Jr.
  • Monitoring structure
    Patent number: 7866224
    Abstract: Apparatus is provided for determining presence of contamination on a lithography mask, including: a fluid trap having a base and at least one wall member extending substantially perpendicularly to the base for trapping fluid on a portion of the base when fluid introduced during a cleaning process of the mask is removed.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 11, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sia Kim Tan, Gek Soon Chua, Qun Ying Lin, Martin Yeo
  • Integrated circuit package-on-package stacking system
    Patent number: 7868434
    Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: January 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Integrated circuit system for suppressing short channel effects
    Patent number: 7867835
    Abstract: An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated circuit system; forming an opening between the material layer and the first spacer by removing a portion of the material layer, the second spacer, and the second liner to expose the substrate; and forming a source/drain extension and a halo region through the opening.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: January 11, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jae Gon Lee, Elgin Kiok Boone Quek, Young Way Teh, Wenzhi Gao
  • Bioluminogenic assay system for measuring beta-lactamase activity
    Patent number: 7867758
    Abstract: A bioluminogenic assay system including: providing a bioluminogenic substrate incorporating a beta-lactam antibiotic, a bioluminescence initiating compound, and a chemical linkage joining the beta-lactam antibiotic to the bioluminescence initiating compound; exposing the bioluminogenic substrate to a beta-lactamase enzyme that catalyzes the release of the bioluminescence initiating compound from the bioluminogenic substrate; co-exposing the bioluminogenic substrate to a bioluminescence indicator reaction that employs the bioluminescence initiating compound as a substrate; and detecting a light from the bioluminescence indicator reaction as a measure of the activity of the beta-lactamase enzyme.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: January 11, 2011
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Jianghong Rao, Min-kyung So, Hequan Yao
  • Integrated circuit package system with through semiconductor vias and method of manufacture thereof
    Patent number: 7867821
    Abstract: A method of manufacture of an integrated circuit package system including: providing a package substrate; mounting a first integrated circuit die, having through silicon vias, on the package substrate; coupling cylindrical studs to the package substrate adjacent to the first integrated circuit die; and mounting a second integrated circuit die, having through silicon vias, on the first integrated circuit die and the cylindrical studs for forming an electrical connection among the second integrated circuit die, the first integrated circuit die, the package substrate, or a combination thereof.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: January 11, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Chee Keong Chin
  • Integrated circuit package system with molding vents
    Patent number: 7863761
    Abstract: An integrated circuit package system comprising: providing a substrate; attaching an integrated circuit die over the substrate; attaching a connector to the integrated circuit die and the substrate; and forming an encapsulant over the substrate, the integrated circuit die, and the connector and minimizing ambient gas deformation of the substrate to keep the connector from touching another connector.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Dal Jae Lee, Nam Ju Cho, Soo-San Park, Jaepil Kim, Sungpil Hur, Hyeong Kug Jin, JongMin Han, SungJae Lim, HyoungChul Kwon
  • Integrated circuit package system with wire bond pattern
    Patent number: 7863737
    Abstract: An integrated circuit package system including providing a plurality of substantially identical package leads formed in a single row, and attaching bond wires having an offset on adjacent locations of the package leads.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byoung Wook Jang, Hun Teak Lee, Kwang Soon Hwang
  • Integrated circuit packaging system with etched ring and die paddle and method of manufacture thereof
    Patent number: 7863108
    Abstract: A method of manufacture of an integrated circuit packaging system is provided including: forming a D-ring includes half etching a paddle, etching a ring, and etching a tie bar. The tie bar is between the paddle and the ring. The system further includes mounting an integrated circuit die on a central portion of the D-ring, connecting the integrated circuit die and the D-ring, and encapsulating the integrated circuit die and a portion of the D-ring.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Antonio B. Dimaano, Jr., Il Kwon Shim, Sheila Rima C. Magno
  • Package-on-package system with via Z-interconnections
    Patent number: 7863755
    Abstract: A package-on-package system includes: providing an interposer substrate; mounting a base substrate under the interposer substrate and having a first integrated circuit die connected thereto; forming an encapsulant between the interposer substrate and the base substrate, the encapsulant encapsulating the first integrated circuit die; and forming a via z-interconnection extending through the encapsulant and one of the substrates to the other of the substrates.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Taewoo Lee, Sang-Ho Lee, SeungYun Ahn
  • Integrated circuit packaging system with a protrusion on an inner stacking module and method of manufacture thereof
    Patent number: 7863109
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an inner stacking module die; encapsulating the inner stacking module die with an inner stacking module encapsulation to form an inner stacking module, the inner stacking module encapsulation having an inner stacking module protrusion having a planar protrusion surface; and encapsulating at least part of the inner stacking module encapsulation with an encapsulation having a flat top coplanar with the planar protrusion surface or fully encapsulating the inner stacking module encapsulation.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: January 4, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Rui Huang, Heap Hoe Kuan