Patents Represented by Attorney Mikio Ishimaru

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  • Multi-layer package-on-package system
    Patent number: 7977780
    Abstract: A package-on-package system includes: providing a bottom package module incorporating a bottom package substrate; attaching a central internal stacking module, incorporating a central interposer, on top of the bottom package module; placing a spacer on the top surface of the central internal stacking module; mounting a first top package module, incorporating a first top interposer with an opening, on the spacer; and enclosing at least portions of the bottom package module, the central internal stacking module, and the first top package module with an encapsulant.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Jairus Legaspi Pisigan, Zigmund Ramirez Camacho
  • Integrated circuit packaging system with stacked die and method of manufacture thereof
    Patent number: 7977802
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a flip chip die, having a backside protrusion; mounting a wire bond die on the flip chip die, adjacent to the backside protrusion; and mounting an internal stacking module over the backside protrusion and the wire bond die.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Multiple flip-chip integrated circuit package system
    Patent number: 7977579
    Abstract: An integrated circuit package system includes forming a multi-tier substrate, and attaching a plurality of integrated circuits on the multi-tier substrate.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry D. Bathan, Zigmund Ramirez Camacho, Jr., Arnel Trasporto, Jeffrey D. Punzalan
  • Integrated circuit isolation system
    Patent number: 7972921
    Abstract: A method of manufacturing a self-aligned inverted T-shaped isolation structure. An integrated circuit isolation system including providing a substrate, forming a base insulator region in the substrate, growing the substrate to surround the base insulator region, and depositing an insulator column having a narrower width than the base insulator region on the base insulator region.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: July 5, 2011
    Assignees: GlobalFoundries Singapore Pte. Ltd., International Business Machines Corporation
    Inventors: Yung Fu Chong, Zhijiong Luo
  • Integrated circuit package system with conformal shielding and method of manufacture thereof
    Patent number: 7968979
    Abstract: An integrated circuit package system includes: providing a substrate with an integrated circuit mounted thereover; mounting a structure, having ground pads, over the integrated circuit; encapsulating the integrated circuit with an encapsulation while leaving the structure partially exposed; and attaching a conformal shielding to the encapsulation and electrically connected to the grounding pads.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Linda Pei Ee Chua, Byung Tai Do
  • Integrated circuit system with clean surfaces
    Patent number: 7968148
    Abstract: An integrated circuit system includes providing an integrated circuit wafer; applying a first cleaning solution over the integrated circuit wafer; and applying a second cleaning solution over the integrated circuit wafer to prevent or remove a defect resulting from the first cleaning process.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: June 28, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Yin-Min Felicia Goh, Zainab Ismail, Yong Siang Tan, Ling Zhi Tan, Sin Ping Chiew
  • Integrated circuit package system with triple film spacer having embedded fillers and method of manufacture thereof
    Patent number: 7969023
    Abstract: An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Taeg Ki Lim, JaEun Yun, Byung Joon Han
  • Inline integrated circuit system
    Patent number: 7968981
    Abstract: An integrated circuit package system including: providing a leadframe with an integrated circuit mounted thereover; encapsulating the integrated circuit with an encapsulation; mounting an etch barrier below the leadframe; and etching the leadframe.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: June 28, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jae Hak Yee, Junwoo Myung, Byoung Wook Jang, YoungChul Kim
  • Integrated circuit protruding pad package system
    Patent number: 7968377
    Abstract: An integrated circuit package system is provided. A protruding pad is formed on a leadframe. A die is attached to the leadframe. The die is electrically connected to the leadframe. At least portions of the leadframe, the protruding pad, and the die are encapsulated in an encapsulant.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Ming Ying, Il Kwon Shim, Roger Emigh
  • Integrated circuit package system with supported stacked die
    Patent number: 7968996
    Abstract: An integrated circuit package system provides a leadframe having a short lead finger, a long lead finger, and a support bar. A first die is placed in the leadframe. An adhesive is attached to the first die, the long lead finger, and the support bar. A second die is offset from the first die. The offset second die is attached to the adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Integrated circuit package on package system
    Patent number: 7968373
    Abstract: An integrated circuit package on package system including: forming a first substrate assembly; forming a second substrate, having an auxiliary access port, supported by the first substrate assembly; exposing an integrated circuit die through the auxiliary access port; and coupling an external integrated circuit on the second substrate.
    Type: Grant
    Filed: May 2, 2008
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, JooSang Kim, DongSoo Moon
  • Integrated circuit packaging system with package-on-package and method of manufacture thereof
    Patent number: 7968995
    Abstract: A method of manufacture an integrated circuit packaging system includes: providing a base substrate; mounting a first base integrated circuit over the base substrate; mounting a second base integrated circuit over the first base integrated circuit; attaching a stacking interconnect to the base substrate and adjacent to the first base integrated circuit; and forming a base encapsulation, having a recess portion from a corner of the base encapsulation and a step portion adjacent to the recess portion, with the step portion over the second base integrated circuit and the recess portion exposing the stacking interconnect.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Chan Hoon Ko, Soo-San Park, HeeJo Chi
  • Semiconductor package system with cavity substrate
    Patent number: 7968371
    Abstract: A semiconductor package system is provided including providing a cavity substrate having a cavity provided therein, attaching a metal die pad to the cavity substrate, attaching a semiconductor die in the cavity to the metal die pad, and attaching solder connectors to the cavity substrate for connection on the system board with the metal die pad on the system board.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: June 28, 2011
    Assignee: STATS ChipPAC Ltd.
    Inventors: OhSug Kim, DeaWhan Kim, SangJo Kim
  • Integrated circuit system employing stress memorization transfer
    Patent number: 7964894
    Abstract: An integrated circuit system that includes: a substrate including a source/drain region defined by a spacer; a gate over the substrate; a gate dielectric between the gate and the substrate; a recrystallized region within the gate and the source/drain region; and a channel exhibiting the characteristics of stress memorization.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: June 21, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Elgin Kiok Boone Quek, Pradeep Ramachandramurthy Yelehanka
  • Semiconductor package with passive device integration
    Patent number: 7960816
    Abstract: A system is provided for an integrated circuit package including a leadframe with a lead finger. A groove is in a lead finger for a conductive bonding agent and a passive device is in the groove to be held by the conductive bonding agent.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: June 14, 2011
    Assignee: ST Assembly Test Services Ltd.
    Inventors: Seng Guan Chow, Il Kwon Shim, Ming Ying, Byung Hoon Ahn
  • Method of manufacture an integrated circuit system with through silicon via
    Patent number: 7960282
    Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including an active device; forming a through-silicon-via into the substrate; forming an insulation layer over the through-silicon-via to protect the through-silicon-via; forming a contact to the active device after forming the insulation layer; and removing the insulation layer.
    Type: Grant
    Filed: May 21, 2009
    Date of Patent: June 14, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Pradeep Ramachandramurthy Yelehanka, Denise Tan, Chung Meng Lek, Thomas Thiam, Jeffrey C. Lam, Liang-Choo Hsia
  • Stacked integrated circuit package system
    Patent number: 7956449
    Abstract: A stacked integrated circuit package system includes: forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit and an interior cavity in the first encapsulation; forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: June 7, 2011
    Assignee: STATS Chippac Ltd.
    Inventors: KyungHoon Lee, Oh Han Kim
  • Integrated circuit packaging system and method of manufacture thereof
    Patent number: 7952176
    Abstract: A method of manufacture of an integrated circuit packaging system includes providing an integrated circuit having an active side and a non-active side; forming a channel through the integrated circuit; forming an indent, having a flange and an indent side, from a peripheral region of the non-active side; and forming a conformal interconnect, having an offset segment, a sloped segment, and a flange segment, under the indent.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: May 31, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Linda Pei Ee Chua
  • Integrated circuit system employing an elevated drain
    Patent number: 7951680
    Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: May 31, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Guowei Zhang, Yisuo Li, Ming Li, Purakh Raj Verma, Shao-fu Sanford Chu
  • Integrated circuit packaging system with lead frame and method of manufacture thereof
    Patent number: 7951643
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a base substrate; attaching a base device over the base substrate; attaching a leadframe having a leadframe pillar adjacent the base device over the base substrate; applying a base encapsulant over the base device, the base substrate, and the leadframe; and removing a portion of the base encapsulant and a portion of the leadframe providing the leadframe pillar partially exposed.
    Type: Grant
    Filed: November 29, 2008
    Date of Patent: May 31, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, TaeWoo Kang, DongSoo Moon