Patents Represented by Attorney Mikio Ishimaru

Find this attorney in the Justia Lawyer Directory

  • Integrated circuit package system for stackable devices
    Patent number: 7919871
    Abstract: An integrated circuit package system includes: providing a lower interposer substrate with lower exposed conductors; attaching a die over the lower interposer substrate; applying a stack encapsulant over the die and the lower interposer substrate having the lower exposed conductors partially exposed adjacent the stack encapsulant; and attaching an upper interposer substrate having upper exposed conductors over the stack encapsulant and with the upper exposed conductors substantially exposed.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: April 5, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DongSoo Moon, Sungmin Song
  • Integrated circuit package system with multiple devices
    Patent number: 7919848
    Abstract: An integrated circuit package system includes: forming a die-attach paddle, an outer interconnect, and an inner interconnect toward the die-attach paddle beyond the outer interconnect; mounting an integrated circuit device over the die-attach paddle; connecting the integrated circuit device to the inner interconnect and the outer interconnect; encapsulating the integrated circuit device over the die-attach paddle; attaching an external interconnect under the outer interconnect; and attaching a circuit device under the die-attach paddle and extended laterally beyond opposite sides of the die-attach paddle.
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: April 5, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry Descalzo Bathan, Abelardo Jr Hadap Advincula, Lionel Chien Hui Tay
  • Stackable multi-chip package system with support structure
    Patent number: 7915738
    Abstract: A stackable multi-chip package system is provided including forming an external interconnect, having a base and a tip, and a paddle; mounting a first integrated circuit die over the paddle; stacking a second integrated circuit die over the first integrated circuit die in a active side to active side configuration; connecting the first integrated circuit die and the base; connecting the second integrated circuit die and the base; and molding the first integrated circuit die, the second integrated circuit die, the paddle, and the external interconnect with the external interconnect partially exposed.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Young Cheol Kim, Koo Hong Lee, Jae Hak Yee
  • Integrated circuit packaging system with base structure device
    Patent number: 7915724
    Abstract: An integrated circuit packaging system including: forming a base structure, having an opening; mounting a base structure device in the opening; attaching an integrated circuit device over the base structure device; and molding an encapsulant on the base structure, the base structure device, and the integrated circuit device.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: March 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jong-Woo Ha, Koo Hong Lee, Soo Won Lee, JuHyun Park, Zigmund Ramirez Camacho, Jeffrey D. Punzalan, Lionel Chien Hui Tay, Jairus Legaspi Pisigan
  • Integrated circuit package system with leadframe array
    Patent number: 7915716
    Abstract: An integrated circuit package system includes providing an integrated circuit die; attaching the integrated circuit die over a lead grid having lead blocks; and connecting a die interconnect to the integrated circuit die and the lead blocks.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Jairus Legaspi Pisigan, Jeffrey D. Punzalan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho
  • Integrated circuit packaging system having planar interconnect
    Patent number: 7911070
    Abstract: An integrated circuit package system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: March 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Heap Hoe Kuan
  • Semiconductor package system with die support pad
    Patent number: 7911067
    Abstract: A semiconductor package system includes: providing a lead frame with a lead; making a die support pad separately from the lead frame; attaching a semiconductor die to the die support pad through a die attach adhesive, the semiconductor die being spaced from the lead; and connecting a bonding pad on the semiconductor die to the lead using a bonding wire.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Dioscoro A. Merilo, Lionel Chien Hui Tay
  • Method of manufacturing a semiconductor package with fine pitch lead fingers
    Patent number: 7909233
    Abstract: A method for manufacturing a semiconductor package system includes: providing a die having a plurality of contact pads; forming a leadframe having a plurality of lead fingers with flat tops of predetermined lengths, the plurality of lead fingers having a fine pitch and each having a trapezoidal cross-section; attaching a plurality of bumps to the plurality of lead fingers, the plurality of bumps on the tops, extending beyond the widths of the trapezoidal cross-sections, and clamping down on the two sides of each of the plurality of lead fingers; attaching a plurality of bond wires to the plurality of contact pads; attaching the plurality of bond wires to the plurality of bumps; and forming an encapsulant over the plurality of lead fingers, the die, and the plurality of bond wires, the encapsulant leaving lower surfaces of the plurality of lead fingers exposed.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: March 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Integrated circuit package with improved connections
    Patent number: 7911040
    Abstract: An integrated circuit package system comprising: providing an integrated circuit die; forming a top paddle over the integrated circuit die wherein the top paddle has planar dimensions smaller than planar dimensions of the integrated circuit die; forming leads adjacent the top paddle; attaching first connectors to the integrated circuit die and the top paddle; attaching second connectors to the integrated circuit die and the leads; and forming an encapsulant over the first connectors, the second connectors, the integrated circuit die, and the top paddle.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: March 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Lionel Chien Hui Tay, Henry Descalzo Bathan, Zigmund Ramirez Camacho
  • Integrated circuit packaging system with interposer
    Patent number: 7911046
    Abstract: An integrated circuit packaging system is provided including forming an interposer having a coupling slot, securing an upper die on the interposer, mounting the interposer over an integrated circuit, and coupling the integrated circuit to the upper die through the coupling slot.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Philip Lyndon Cablao, Rachel Layda Abinan, Dario S. Filoteo, Jr., Allan P. Ilagan
  • Integrated circuit package system with interconnection support and method of manufacture thereof
    Patent number: 7901996
    Abstract: An integrated circuit package system with interconnect support is provided including providing an integrated circuit, forming an electrical interconnect on the integrated circuit, forming a contact pad having a chip support, and coupling the integrated circuit to the contact pad by the electrical interconnect, with the integrated circuit on the chip support.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: March 8, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Il Kwon Shim, Jeffrey D. Punzalan, Zigmund Ramirez Camacho
  • Package-on-package system with internal stacking module interposer
    Patent number: 7901987
    Abstract: A package-on-package system includes: forming a first integrated circuit package including second top electrical contacts and first external electrical contacts on opposite sides thereof; forming an internal stacking module interposer including first top electrical contacts and base electrical connectors on opposite sides thereof; attaching the internal stacking module interposer to the first integrated circuit package with the first top electrical contacts connected to the second top electrical contacts; and molding a package encapsulant over the first integrated circuit package and around the internal stacking module interposer leaving a package encapsulant cavity for attaching a stacked package to the base electrical connectors.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: March 8, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Joungin Yang, Dongjin Jung
  • Integrated circuit package system for electromagnetic isolation
    Patent number: 7902644
    Abstract: An integrated circuit package system comprising: providing a lead frame; forming an integrated circuit package including the lead frame; providing a selectively exposed area on the lead frame; and coating a conductive shielding layer on the integrated circuit package for coupling the selectively exposed area.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: March 8, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Rui Huang, Byung Tai Do, Seng Guan Chow, Heap Hoe Kuan
  • Planar voltage contrast test structure
    Patent number: 7902548
    Abstract: An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned in the space. Structures for detecting open circuits and short circuits are described.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: March 8, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Seng-Keong Victor Lim, Dennis Tan, Tze Ho Simon Chan
  • Package stacking system with mold contamination prevention
    Patent number: 7898072
    Abstract: A package stacking system includes: providing a package substrate; mounting an integrated circuit over the package substrate; forming a step-down interposer over the integrated circuit; and molding a stack package body, having a step profile, on the package substrate and the step-down interposer.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: March 1, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: YoungJoon Kim, YoRim Lee
  • Integrated circuit packaging system and method of manufacture thereof
    Patent number: 7892963
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an integrated circuit substrate having a non-active side and an active side; forming a recess in the integrated circuit substrate from the non-active side exposing a first contact and a second contact with the first contact and the second contact along the active side; forming a first via, having a first via extension extended beyond the non-active side and an opening at the non-active side, within the recess; forming a barrier liner within the opening with the barrier liner exposed beyond the non-active side; and forming a second via over the barrier liner and within the opening of the first via with the second via exposed beyond the non-active side.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: February 22, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Alfred Yeo, Kai Chong Chan
  • Method of manufacturing integrated circuit package system with warp-free chip
    Patent number: 7892894
    Abstract: An integrated circuit package system includes: providing an integrated circuit wafer having an active side and a backside; forming a stress-relieving layer on the backside; forming an adhesion layer on the stress-relieving layer; dicing the integrated circuit wafer into a semiconductor chip with the stress-relieving layer and the adhesion layer on the backside of the semiconductor chip; and mounting the semiconductor chip over electrical interconnects.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: February 22, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Il Kwon Shim, Antonio B. Dimaano, Jr., Heap Hoe Kuan
  • Integrated circuit system employing sacrificial spacers
    Patent number: 7892900
    Abstract: An integrated circuit system that includes: providing a substrate including a first device and a second device; configuring the first device and the second device to include a first spacer, a first liner made from a first dielectric layer, and a second spacer made from a sacrificial spacer material; forming a second dielectric layer over the integrated circuit system; forming a first device source/drain and a second device source/drain adjacent the second spacer and through the second dielectric layer; removing the second spacer without damaging the substrate; forming a third dielectric layer over the integrated circuit system before annealing; and forming a fourth dielectric layer over the integrated circuit system that promotes stress within the channel of the first device, the second device, or a combination thereof.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: February 22, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Huang Liu, Wei Lu, Hai Cong, Alex K. H. See, Hui Peng Koh, Meisheng Zhou
  • Test system with user selectable channel
    Patent number: 7885195
    Abstract: A test system comprising: acquiring an upstream channel descriptor list; entering a pause network state when the upstream channel descriptor list is completed; and selecting a particular channel from the upstream channel descriptor list before exiting the pause network state.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: February 8, 2011
    Assignee: Sunrise Telecom Incorporated
    Inventors: Brady Volpe, Matt DuBose, Marco Laburada
  • Integrated circuit packaging system with carrier and method of manufacture thereof
    Patent number: 7884460
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a carrier having a top side and a bottom side; forming an edge terminal pad on the top side and an inner terminal pad on the bottom side; connecting an integrated circuit die to an inner portion of the edge terminal pad; and encapsulating the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: February 8, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Choong Bin Yim, Hyeog Chan Kwon, Jong-Woo Ha