Patents Represented by Attorney Mikio Ishimaru

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  • Integrated circuit package system with laminate base
    Patent number: 7993939
    Abstract: An integrated circuit package system with laminate base is provided including forming a base package including, forming a laminate substrate strip, mounting an integrated circuit on the laminate substrate strip, forming a molded cover over the integrated circuit and the laminate substrate strip, and performing a strip test of the base package; attaching a bare die to the base package; connecting electrically the bare die to the laminate substrate strip; and encapsulating the bare die and the base package.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: August 9, 2011
    Assignee: STATS Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Integrated circuit package system with wire-in-film isolation barrier
    Patent number: 7994645
    Abstract: An integrated circuit package in package system includes: providing a substrate having a first wire-bonded die with an active side mounted above; connecting the active side of the first wire-bonded die to the substrate with a bond-wire; mounting a wire-in-film adhesive having an isolation barrier over the first wire-bonded die; and encapsulating the first wire-bonded die, the bond-wires, and the wire-in-film adhesive with an encapsulation.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Jonathan Abela
  • Leadless integrated circuit packaging system and method of manufacture thereof
    Patent number: 7994629
    Abstract: A method of manufacture of a leadless integrated circuit packaging system includes: providing a substrate; patterning a die attach pad on the substrate; forming a tiered plated pad array around the die attach pad; mounting an integrated circuit die on the die attach pad; coupling an electrical interconnect between the integrated circuit die and the tiered plated pad array; forming a molded package body on the integrated circuit die, the electrical interconnects, and the tiered plated pad array; and exposing a contact pad layer by removing the substrate.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Integrated circuit packaging system having an internal structure protrusion and method of manufacture thereof
    Patent number: 7994625
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing an internal structure substrate having an internal structure substrate cavity; mounting an internal structure die above the internal structure substrate; encapsulating the internal structure die with an internal structure encapsulation to form an internal structure package; forming an internal structure protrusion in the internal structure encapsulation below the internal structure substrate cavity; mounting the internal structure package above a substrate; and encapsulating the internal structure package above the substrate with an encapsulation.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DaeSik Choi, DeokKyung Yang, Jong-Woo Ha, Byoung Wook Jang, JaeSick Bae, Seung Won Kim
  • Bridge stack integrated circuit package system
    Patent number: 7994619
    Abstract: An integrated circuit package system is provided including mounting a first device on a carrier, mounting a second device over the first device and the carrier in an offset face-to-face configuration, and connecting the first device and the second device at an overlap.
    Type: Grant
    Filed: November 1, 2006
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Richard P. Sheridan, Eric Gongora, Douglas J. Mathews
  • Leadless package system having external contacts
    Patent number: 7993979
    Abstract: A leadless package system includes: providing a chip carrier having indentations defining a pattern for a protrusion for external contact terminals; placing an external coating layer in the indentations in the chip carrier; layering a conductive layer on top of the external coating layer; depositing an internal coating layer on the conductive layer; patterning the internal coating layer and the conductive layer to define external contact terminals with a T-shape profile; connecting an integrated circuit die to the external contact terminals; encapsulating the integrated circuit die and external contact terminals; and separating the chip carrier from the external coating layer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Heap Hoe Kuan
  • Integrated circuit package system with adhesive segment spacer
    Patent number: 7994624
    Abstract: An integrated circuit package system includes attaching an adhesive segment spacer to an interposer assembly; mounting an integrated circuit over a carrier; mounting the interposer assembly over the integrated circuit with the adhesive segment spacer exposing an inner region of the integrated circuit and covering a periphery of the integrated circuit; and forming an encapsulation over the integrated circuit, the interposer assembly, and the adhesive segment spacer with the interposer assembly exposed with a recess in the encapsulation.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: August 9, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Linda Pei Ee Chua, Byung Tai Do, Reza Argenty Pagaila
  • Integrated circuit package system with support structure for die overhang
    Patent number: 7989941
    Abstract: An integrated circuit package system including: providing a substrate having a support mounted thereover; mounting an integrated circuit die above the substrate; mounting a wire-bonded die offset above the integrated circuit die creating an overhang supported by the support; connecting the wire-bonded die to the substrate with bond wires; and encapsulating the integrated circuit die, the wire-bonded die and the bond wires with an encapsulation.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 2, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Chee Keong Chin, Guo Qiang Shen, Ya Ping Wang
  • Integrated circuit packaging system having a cavity
    Patent number: 7989950
    Abstract: An integrated circuit packaging system includes: attaching a carrier, having a carrier top side and a carrier bottom side, and an interconnect without an active device attached to the carrier bottom side; and forming a first encapsulation, having a cavity, around the interconnect over the carrier top side with the interconnect partially exposed from the first encapsulation and with the carrier top side partially exposed with the cavity.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: August 2, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DongSam Park, Dongjin Jung
  • Integrated circuit package system with under paddle leadfingers
    Patent number: 7989931
    Abstract: An integrated circuit package system is provided including: forming a die paddle; forming an under paddle leadframe including lower leadfingers thereon; attaching the under paddle leadframe to the die paddle with the lower leadfingers extending under the die paddle; attaching a die to the die paddle; and planarizing the bottom surface of the under paddle leadframe to separate the lower leadfingers under the die paddle.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 2, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Guruprasad Badakere Govindaiah, Arnel Trasporto
  • Package-on-package system with through vias and method of manufacture thereof
    Patent number: 7986048
    Abstract: A method of manufacture of a package-on-package system includes: providing a package substrate; attaching a semiconductor die to the package substrate; forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the package substrate and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface; and creating through vias by applying solder into the through openings.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: July 26, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: DongSam Park, JoungIn Yang
  • Integrated circuit package system with interconnect lock
    Patent number: 7985628
    Abstract: An integrated circuit package system includes: mounting a device structure over a package carrier; connecting an internal interconnect between the device structure and the package carrier; forming an interconnect lock over the internal interconnect over the device structure with interconnect lock exposing the device structure; and forming a package encapsulation adjacent to the interconnect lock and over the package carrier.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: July 26, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Seng Guan Chow, Linda Pei Ee Chua, Dioscoro A. Merilo
  • Integrated circuit package on package system
    Patent number: 7986043
    Abstract: An integrated circuit package on package system including forming an interconnect integrated circuit package and attaching an extended-lead integrated circuit package on the interconnect integrated circuit package wherein a mold cap of the extended-lead integrated circuit package faces a mold cap of the interconnect integrated circuit package.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: July 26, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano, Jr., Heap Hoe Kuan, Tsz Yin Ho
  • Integrated circuit package system with contoured encapsulation
    Patent number: 7985623
    Abstract: An integrated circuit package system is provided including providing a carrier, mounting an integrated circuit die on the carrier, connecting the integrated circuit die with the carrier, and forming an encapsulation having a multi-sloped side over the integrated circuit die for reducing ejection stress.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: July 26, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Choong Bin Yim, Young Cheol Kim
  • Semiconductor package system with substrate having different bondable heights at lead finger tips
    Patent number: 7986032
    Abstract: A semiconductor package system is provided. A substrate having a die attach paddle is provided. A first plurality of leads is provided around the die attach paddle having a first plurality of lead tips. A second plurality of leads is provided around the die attach paddle interleaved with the first plurality of leads, at least some of the second plurality of leads having a plurality of depression lead tips. A first die is attached to the die attach paddle. The die is wire bonded to the first plurality of leads and the second plurality of leads. The die is encapsulated.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: July 26, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Ming Ying, Ii Kwon Shim, Lip Seng Tan
  • Integrated circuit package in package system
    Patent number: 7981702
    Abstract: An integrated circuit package in package system including forming a base integrated circuit package with a base lead having a portion with a substantially planar base surface, forming an extended-lead integrated circuit package with an extended lead having a portion with a substantially planar lead-end surface, and stacking the extended-lead integrated circuit package over the base integrated circuit package with the substantially planar lead-end surface coplanar with the substantially planar base surface.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: July 19, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Tsz Yin Ho, Dioscoro A. Merilo, Seng Guan Chow, Antonio B. Dimaano, Jr., Heap Hoe Kuan
  • Mountable integrated circuit package-in-package system
    Patent number: 7977779
    Abstract: A mountable integrated circuit package-in-package system includes: providing an interface integrated circuit package system with a terminal having a plated bumped portion of an inner encapsulation; mounting the interface integrated circuit package system over a package carrier with the terminal facing away from the package carrier; connecting the package carrier and a pad extension of the terminal; and forming a package encapsulation over the interface integrated circuit package system with the terminal exposed.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Arnel Senosa Trasporto, Lionel Chien Hui Tay, Henry Descalzo Bathan
  • Integrated circuit package system with dual connectivity
    Patent number: 7977782
    Abstract: An integrated circuit package system includes: forming a lead having a both top contact portion and a bottom contact portion; connecting an integrated circuit die and the lead; and forming a package encapsulation, having a top side and a bottom side, over the integrated circuit die. The forming the package encapsulation includes partially exposing the top contact portion at the top side, and partially exposing the bottom contact portion along the bottom side with the bottom contact portion extending beyond a nonhorizontal portion of the package encapsulation.
    Type: Grant
    Filed: November 7, 2007
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Jairus Legaspi Pisigan, Jose Alvin Caparas, Lionel Chien Hui Tay
  • Wafer scale heat slug system
    Patent number: 7975377
    Abstract: A wafer scale heat slug system is presented providing dicing an integrated circuit from a semiconductor wafer, forming a heat slug blank equivalent in size to the semiconductor wafer, dicing the heat slug blank to produce a heat slug equivalent in size to the integrated circuit, attaching the integrated circuit to a substrate, attaching the heat slug to the integrated circuit and encapsulating the integrated circuit.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventor: Hyeog Chan Kwon
  • Integrated circuit package system with interference-fit feature
    Patent number: 7977778
    Abstract: An integrated circuit package system is provided including forming an integrated circuit die, forming an interference-fit feature in the integrated circuit die, fitting a support element within the interference-fit feature, connecting an external interconnect and the integrated circuit die, and encapsulating the integrated circuit die.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: July 12, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Henry Descalzo Bathan, Lionel Chien Hui Tay, Zigmund Ramirez Camacho