Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8349661
    Abstract: The yield of semiconductor devices is improved. In an upper die of a resin molding die including a pair of the upper die and a lower die, by lengthening the radius of the cross section of an inner peripheral surface of a second corner part facing an injection gate of a cavity more than that of the other corner part, a void contained in a resin in resin injection can be pushed out into an air vent without allowing the void to remain in the second corner part of the cavity. Consequently, the occurrence of the void in the cavity can be prevented and then the occurrence of the appearance defect of the semiconductor device can be prevented.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Makio Okada, Hidetoshi Kuraya, Toshio Tanabe, Yoshinori Fujisaki, Kotaro Arita
  • Patent number: 8351254
    Abstract: The performance of a semiconductor device including a nonvolatile memory is enhanced. Each of nonvolatile memory cells arranged over a silicon substrate includes: a first n-well; a second n-well formed in a place different from the place thereof; a selection transistor formed in the first n-well; and an electric charge storage portion having a floating gate electrode and a storage portion p-well. The floating gate electrode is so placed that it overlaps with part of the first n-well and the second n-well. The storage portion p-well is placed in the first n-well so that it partly overlaps with the floating gate electrode. In this nonvolatile memory cell, memory information is erased by applying positive voltage to the second n-well to discharge electrons in the floating gate electrode to the second n-well.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuhiro Taniguchi
  • Patent number: 8350301
    Abstract: A semiconductor photodiode includes a semiconductor substrate; a first conduction type first semiconductor layer formed above the semiconductor substrate; a high resistance second semiconductor layer formed above the first semiconductor layer; a first conduction type third semiconductor layer formed above the second semiconductor layer; and a second conduction type fourth semiconductor layer buried in the second semiconductor layer, in which the fourth semiconductor layer is separated at a predetermined distance in a direction horizontal to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Shinichi Saito, Youngkun Lee, Katsuya Oda
  • Patent number: 8351311
    Abstract: The present invention achieves higher precision and lower power consumption by reducing semiconductor chip occupation area. A semiconductor integrated circuit which can be mounted on an optical disk device has: a wobble signal generating circuit capable of receiving first, second, third, and fourth light reception output signals A, B, C, and D of a light receiving element in an optical pickup and detecting a wobble in a recordable disk; a differential phase detection signal (DPD) generating circuit for tracking an unrecordable disk; and two A/D converters and an arithmetic circuit.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiya Matsuda, Hiroshi Ide
  • Patent number: 8352096
    Abstract: The present invention provides an arrangement for enabling a plurality of central processing units to share specific resources while ensuring overall reliability owing to domain separation.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Seiichi Saito, Katsuo Kanemaru, Takahiro Oga
  • Patent number: 8351255
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics COrporation
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Patent number: 8350328
    Abstract: Characteristics of a semiconductor device having a FINFET are improved. The FINFET has: a channel layer arranged in an arch shape on a semiconductor substrate and formed of monocrystalline silicon; a front gate electrode formed on a part of an outside of the channel layer through a front gate insulating film; and a back gate electrode formed so as to be buried inside the channel layer through a back gate insulating film. The back gate electrode arranged inside the arch shape is arranged so as to pass through the front gate electrode.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Ishigaki, Ryuta Tsuchiya, Yusuke Morita, Nobuyuki Sugii
  • Patent number: 8347459
    Abstract: A hinge (1) has a carcass-side hinge portion (4) which can be pre-mounted on a furniture carcass (2) and a hinge portion (6) which can he pre-mounted on a door wing (3), the hinge portions (4, 6) being joined together in an articulated manner and at least one of the hinge portions (4, 6) having height adjustment means (10) and/or a lateral adjustment means (5). The hinge portion (6) mounted on the door has a hinge cup (8) in which the height adjustment means (10) are arranged, and at least one locking element (17) for immobilising the door wing (3) in relation to the furniture carcass (2) at the set vertical position of the door wing (3).
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: January 8, 2013
    Assignee: PRÄMETA GmbH & Co. KG
    Inventor: Rolf Heisig
  • Patent number: 8351867
    Abstract: The present invention provides an oscillator and a communication system using the oscillator, in particular, an LC oscillator adapted to lessen phase noise deterioration due to harmonic distortions and increase the amplitude of oscillation, thereby having a favorable low phase noise characteristic. The oscillator comprises at least one voltage to current converter consisting of a transistor and a resonator comprising two LC tanks consisting of a pair of conductive elements and inductive elements. A feedback loop is formed such that an output terminal of the voltage to current converter is connected to the resonator and a current input to the resonator is converted to a voltage which is in turn fed back to an input terminal of the voltage to current converter. Inductive elements constituting the two LC tanks constituting the resonator are mutually inductively couple and a coefficient of the mutual induction is about ?0.6.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Yusuke Wachi
  • Patent number: 8351283
    Abstract: The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased.
    Type: Grant
    Filed: June 13, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Masao Shinozaki, Hajime Sato
  • Patent number: 8350311
    Abstract: The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kaneko, Hiroyasu Noso, Katsuhiko Hotta, Shinichi Ishida, Hidenori Suzuki, Sadayoshi Tateishi
  • Patent number: 8350595
    Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Masafumi Onouchi
  • Patent number: 8350832
    Abstract: The semiconductor IC device for display control disclosed herein aims to achieve a higher rate of memory access cycles without enhancing the current carrying capability of the memory device. The IC device is provided with a memory cell array capable to store display data, peripheral circuits to enable writing and reading of display data, and a control circuit which is able to control read and write operations from/to the memory cell array. The memory cell array comprises a plurality of memory blocks. The control circuit comprises a control logic which enables parallel processing of write operations in such a manner that, before completion of writing of data to one of the memory blocks, writing of data to another memory block is started. Write cycles are shortened by the parallel processing of write operations.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hirofumi Sonoyama, Sosuke Tsuji, Hikaru Shibahara
  • Patent number: 8350325
    Abstract: A problem associated with n-channel power MOSFETs and the like that the following is caused even by relatively slight fluctuation in various process parameters is solved: source-drain breakdown voltage is reduced by breakdown at an end of a p-type body region in proximity to a portion in the vicinity of an annular intermediate region between an active cell region and a chip peripheral portion, arising from electric field concentration in that area. To solve this problem, the following measure is taken in a power semiconductor device having a superjunction structure in the respective drift regions of a first conductivity type of an active cell region, a chip peripheral region, and an intermediate region located therebetween: the width of at least one of column regions of a second conductivity type comprising the superjunction structure in the intermediate region is made larger than the width of the other regions.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Tomohiro Tamaki, Yoshito Nakazawa
  • Patent number: 8350409
    Abstract: Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires. In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Masanao Yamaoka, Kenichi Osada, Yasuhiro Fujimura, Tetsuya Fukuoka, Ryo Nishino
  • Patent number: 8350986
    Abstract: A backlight unit of thin-type comprises: at least one or more light source(s); plural numbers of light guide plates, each of which is configured to guide and irradiate the light of the light source(s) to a side of a liquid crystal panel; and a chassis, on which the light source(s) and the light guide plates are fixed, thereby being constructed by aligning the light guide plates, wherein the following conditions are satisfied: 15.0 mm>h, 20°???60° when assuming that a distance from an irradiation surface of the backlight unit to the light guide plate is “h”, and that an angle indicative of a half-value light intensity of a light emitting from a light emission surface of the light guide plate, thereby providing a video of high picture quality, and there is also provided a video display apparatus applying the same therein.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: January 8, 2013
    Assignee: Hitachi Consumer Electronics Co., Ltd.
    Inventors: Satoshi Ouchi, Hajime Inoue, Hidenao Kubota, Mayumi Nagayoshi
  • Patent number: 8350372
    Abstract: The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS•FET for a high side switch and a power MOS•FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.
    Type: Grant
    Filed: February 13, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Satou, Tomoaki Uno, Nobuyoshi Matsuura, Masaki Shiraishi
  • Patent number: 8346180
    Abstract: A transceiver includes an oscillator and a plurality of communication blocks. Each of the communication blocks includes frequency dividers and mixers. Frequency dividing number of the frequency divider included in one communication block is set to an even-numbered integer, and transmission local signals supplied from the frequency dividers to the mixer become quadrature signals having a phase difference of 90 degrees. The frequency dividing number of another frequency divider in the another communication block is set to a non-integer, and communication local signals supplied from the frequency divider to the mixers become non-quadrature signals having a phase difference at a predetermined offset angle from 90 degrees. The transceiver further includes a converting unit for giving a compensation offset amount having almost the same absolute value and having a polarity opposite to that of the offset angle to communication analog signals related to the mixer of the another communication block.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: January 1, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Kamizuma, Satoshi Tanaka, Taizo Yamawaki, Yukinori Akamine, Koji Maeda
  • Patent number: 8346577
    Abstract: Described are computer-based methods and apparatuses, including computer program products, for automation of auditing claims. A data file is received comprising one or more auditable items, each auditable item comprising a word string having one or more words. Each word string for each auditable item is translated using one or more translation steps into a translated item description. Each translated item description is compared to a plurality of terms to generate matching information. Each translated item description is associated with an item identifier based on the matching information. Each auditable item is accepted or rejected based on the item identifier and one or more rules associated with the data file.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: January 1, 2013
    Assignee: HyperQuest, Inc.
    Inventors: Dennis M. Hogan, Jeffrey J. Hogan
  • Patent number: 8346683
    Abstract: A knowledge based system, program, and method for regulatory knowledge representation, utilization, and maintenance is presented. The system, program, and method support advanced reasoning concerning entities and events in order to determine their adherence to regulations and policies, with the specific ability to identify violations of regulations that govern industries such as the financial services industry. Advanced approaches and methods that allow for efficient representation of regulatory knowledge, its utilization and maintenance are specifically defined. Events and actions like, for instance, financial transactions or regulatory compliance violations can be evaluated on an automated basis by applying various approaches and methods using the regulatory knowledge system.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: January 1, 2013
    Assignee: Exprentis, Inc.
    Inventors: Tomasz G. Dybala, Ewa Grzybowska, Roman Vichr