Patents Represented by Attorney Miles & Stockbridge P.C.
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Patent number: 8351867Abstract: The present invention provides an oscillator and a communication system using the oscillator, in particular, an LC oscillator adapted to lessen phase noise deterioration due to harmonic distortions and increase the amplitude of oscillation, thereby having a favorable low phase noise characteristic. The oscillator comprises at least one voltage to current converter consisting of a transistor and a resonator comprising two LC tanks consisting of a pair of conductive elements and inductive elements. A feedback loop is formed such that an output terminal of the voltage to current converter is connected to the resonator and a current input to the resonator is converted to a voltage which is in turn fed back to an input terminal of the voltage to current converter. Inductive elements constituting the two LC tanks constituting the resonator are mutually inductively couple and a coefficient of the mutual induction is about ?0.6.Type: GrantFiled: March 3, 2010Date of Patent: January 8, 2013Assignee: Hitachi, Ltd.Inventor: Yusuke Wachi
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Patent number: 8350409Abstract: Objects of the invention are to minimize power consumption while maintaining the required information processing capabilities of an LSI chip by supplying multiple voltages to the LSI chip such that its circuit blocks receive necessary voltages and to prevent an increase in the chip area of the LSI chip and performance degradation of signal wires, which may result from the supply of the multiple voltages, by reducing the number of power supply wires. In an LSI chip to which two voltages are supplied, high voltage wires are more densely spaced than low voltage wires. By selectively applying voltages based on circuit block performance, it is possible to reduce power consumption while maintaining the amount of information processed by the LSI chip.Type: GrantFiled: April 13, 2010Date of Patent: January 8, 2013Assignee: Hitachi, Ltd.Inventors: Masanao Yamaoka, Kenichi Osada, Yasuhiro Fujimura, Tetsuya Fukuoka, Ryo Nishino
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Patent number: 8350311Abstract: The present invention provides a technology capable of providing a semiconductor device having an MIM structure capacitor with improved reliability. The capacitor has a lower electrode, a capacitor insulating film, and an upper electrode. The lower electrode is comprised of a metal film embedded in an electrode groove formed in an insulating film over the main surface of a semiconductor substrate; and the upper electrode is comprised of a film stack of a TiN film (lower metal film) and a Ti film (cap metal film) formed over the TiN film (lower metal film).Type: GrantFiled: December 22, 2010Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Yoshiyuki Kaneko, Hiroyasu Noso, Katsuhiko Hotta, Shinichi Ishida, Hidenori Suzuki, Sadayoshi Tateishi
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Patent number: 8350595Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.Type: GrantFiled: April 3, 2012Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Masafumi Onouchi
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Patent number: 8347459Abstract: A hinge (1) has a carcass-side hinge portion (4) which can be pre-mounted on a furniture carcass (2) and a hinge portion (6) which can he pre-mounted on a door wing (3), the hinge portions (4, 6) being joined together in an articulated manner and at least one of the hinge portions (4, 6) having height adjustment means (10) and/or a lateral adjustment means (5). The hinge portion (6) mounted on the door has a hinge cup (8) in which the height adjustment means (10) are arranged, and at least one locking element (17) for immobilising the door wing (3) in relation to the furniture carcass (2) at the set vertical position of the door wing (3).Type: GrantFiled: April 28, 2006Date of Patent: January 8, 2013Assignee: PRÄMETA GmbH & Co. KGInventor: Rolf Heisig
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Patent number: 8352096Abstract: The present invention provides an arrangement for enabling a plurality of central processing units to share specific resources while ensuring overall reliability owing to domain separation.Type: GrantFiled: April 20, 2010Date of Patent: January 8, 2013Assignee: Renesas Electronics CorporationInventors: Seiichi Saito, Katsuo Kanemaru, Takahiro Oga
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System, program, and method for representation, utilization, and maintenance of regulatory knowledge
Patent number: 8346683Abstract: A knowledge based system, program, and method for regulatory knowledge representation, utilization, and maintenance is presented. The system, program, and method support advanced reasoning concerning entities and events in order to determine their adherence to regulations and policies, with the specific ability to identify violations of regulations that govern industries such as the financial services industry. Advanced approaches and methods that allow for efficient representation of regulatory knowledge, its utilization and maintenance are specifically defined. Events and actions like, for instance, financial transactions or regulatory compliance violations can be evaluated on an automated basis by applying various approaches and methods using the regulatory knowledge system.Type: GrantFiled: April 30, 2010Date of Patent: January 1, 2013Assignee: Exprentis, Inc.Inventors: Tomasz G. Dybala, Ewa Grzybowska, Roman Vichr -
Patent number: 8346577Abstract: Described are computer-based methods and apparatuses, including computer program products, for automation of auditing claims. A data file is received comprising one or more auditable items, each auditable item comprising a word string having one or more words. Each word string for each auditable item is translated using one or more translation steps into a translated item description. Each translated item description is compared to a plurality of terms to generate matching information. Each translated item description is associated with an item identifier based on the matching information. Each auditable item is accepted or rejected based on the item identifier and one or more rules associated with the data file.Type: GrantFiled: May 29, 2009Date of Patent: January 1, 2013Assignee: HyperQuest, Inc.Inventors: Dennis M. Hogan, Jeffrey J. Hogan
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Patent number: 8339869Abstract: To improve the speed of accessing a low-speed circuit block from a high-speed circuit block without significantly increasing power consumption.Type: GrantFiled: August 30, 2011Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Yoshihiko Hotta, Seiichi Saito, Hiroyuki Hamasaki, Hirotaka Hara, Itaru Nonomura
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Patent number: 8338968Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.Type: GrantFiled: February 14, 2012Date of Patent: December 25, 2012Assignee: Renesas Electronics CorporationInventors: Akihiko Yoshioka, Shinya Suzuki
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Patent number: 8339713Abstract: A zoom optical system comprising, in order from an object side: a first lens group G1 having positive refractive power; a second lens group G2 having negative refractive power; and a rear lens group GR having positive refractive power; the rear lens group GR including at least a third lens group G3 that is disposed to the most object side and has positive refractive power, the third lens group G3 including at least four positive lenses L31-L33, L35 and at least one negative lens L34, at least a portion of a lens group disposed to an image side of the first lens group G1 being movable as a vibration reduction lens group in a direction including a component perpendicular to an optical axis, and a given conditional expression being satisfied, thereby providing a zoom optical system having excellent optical performance.Type: GrantFiled: September 23, 2010Date of Patent: December 25, 2012Assignee: Nikon CorporationInventor: Hiroki Harada
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Patent number: 8334726Abstract: The semiconductor integrated circuit incorporates a PLL circuit including a phase-frequency comparator 1, first and second charge pumps 2 and 3, a loop filter 4, a voltage-control oscillator 5 and a divider 6. The operation mode of the PLL circuit includes a standby state where locking is stopped, a lock response operation where locking is started and a steady lock operation where the locking started by the lock response operation is continued. In the steady lock operation, setting is made so that the second charge pump 3 is smaller in charge/discharge current than the first charge pump 2. The first and second charge pumps 2 and 3 charge and discharge the loop filter 4 in response to outputs of the phase-frequency comparator 1 in reverse to each other in phase. In the lock response operation where locking is started, the second charge pump 3 is stopped from charging and discharging in reverse in phase.Type: GrantFiled: November 23, 2010Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventor: Takashi Kawamoto
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Patent number: 8335883Abstract: To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register.Type: GrantFiled: August 11, 2010Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventors: Shohei Tateyama, Takao Yamauchi, Eisaku Tomida, Kunihiko Nishiyama, Yasuyuki Suzuki
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Patent number: 8327706Abstract: A high-performance angular rate detecting device is provided. A driving part including a drive frame and a Coriolis frame is levitated by at least two fixing beams which share a fixed end and are extending in a direction orthogonal to a driving direction, thereby vibrating the driving part. Even when a substrate is deformed by mounting or heat fluctuation, internal stress generated to the fixed beam and a supporting beam is small, thereby maintaining a vibrating state such as resonance frequency and vibration amplitude constant. Therefore, a high-performance angular rate detecting device which is robust to changes in mounting environment can be obtained.Type: GrantFiled: July 8, 2010Date of Patent: December 11, 2012Assignee: Hitachi, Ltd.Inventors: Heewon Jeong, Yasushi Goto
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Patent number: 8327840Abstract: A solar energy collection system includes a primary solar receiver and a secondary solar receiver. The secondary solar receiver generates steam using energy from solar radiation incident thereon. The primary solar receiver receives the generated steam from the secondary solar receiver and superheats the steam using energy from solar radiation incident thereon. A plurality of heliostat-mounted mirrors reflects incident solar radiation onto one of the primary and secondary solar receivers. A controller aims a portion of the heliostat-mounted mirrors at the primary solar receiver such that a predetermined thermal profile is provided on a surface of the primary solar receiver.Type: GrantFiled: July 22, 2010Date of Patent: December 11, 2012Assignee: Brightsource Industries (Israel) Ltd.Inventors: Yoel Gilon, Israel Kroizer
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Patent number: 8330524Abstract: A semiconductor integrated circuit which reduces and increase in the level of a harmonic signal of an RF transmission output signal at the time of supplying an RF transmission signal to a bias generation circuit of an antenna switch, including an antenna switch having a bias generation circuit, a transmitter switch, and a receiver switch. The on/off state of a transistor of the transmitter switch coupled between a transmitter port and an I/O port is controlled by a transmit control bias. The on/off state of the transistors of the receiver switch coupled between the I/O port and a receiver port is controlled by a receiver control bias. An RF signal input port of the bias generation circuit is coupled to the transmit port, and a negative DC output bias generated from a DC output port is supplied to a gate control port of transistors of the receiver switch.Type: GrantFiled: March 13, 2012Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Kaoru Katoh, Shigeki Koya, Shinichiro Takatani, Yasushi Shigeno, Akishige Nakajima, Takashi Ogawa
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Patent number: 8327992Abstract: The present invention provides a friction plate having a friction surface formed by sticking an annular friction material to a substantially annular core plate and wherein the friction surface is provided with a first oil groove having an opening portion opened to an inner peripheral edge of the friction plate and an end terminating at a point between the inner peripheral edge and an outer peripheral edge, and a second oil groove having an opening portion opened to the outer peripheral edge of the friction plate and an end terminating at a point between the inner peripheral edge and the outer peripheral edge.Type: GrantFiled: December 30, 2011Date of Patent: December 11, 2012Assignee: NSK-Warner K.K.Inventors: Tomoyuki Miyazaki, Masahiro Kobayashi
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Patent number: 8330688Abstract: A display control drive device sequentially reads display data from a display memory in which the display data is stored, produces three primary color image signals that are applied to pixel locations in a dot-matrix color display device, and transmits the signals through a common external output terminal in a time-sharing manner. The display control drive device produces control signals applied to selection switching elements in the display device and that selectively apply an input image signal to any of three source lines. The display control drive device includes: a unit that determines one horizontal period based on a clock received from outside synchronously with display data; and a signal production circuit that produces and transmits the control signals, applied to the selection switching elements, so that the control signals will have a pulse duration equivalent to a time calculated by trisecting one horizontal period.Type: GrantFiled: November 1, 2010Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Yasuhito Kurokawa, Kunihiko Tani
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Patent number: 8330496Abstract: An object of the present invention is to provide a technique of reducing the leakage current of a drive circuit for driving a circuit that must retain a potential (or information) when in its standby state. A semiconductor integrated circuit device of the present invention includes a drive circuit for driving a circuit block. This drive circuit is made up of a double gate transistor with gates having different gate oxide film thicknesses. When the circuit block is in its standby state, the gate of the double gate transistor having a thinner gate oxide film is turned off and that having a thicker gate oxide film is turned on. This arrangement allows a reduction in the leakage currents of both the circuit block and the drive circuit while allowing the drive circuit to deliver or cut off power to the circuit block.Type: GrantFiled: November 18, 2009Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Masanao Yamaoka, Takayuki Kawahara
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Patent number: D673744Type: GrantFiled: November 7, 2011Date of Patent: January 1, 2013Inventors: Roberto Vela, Jonathan H. Bents