Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8291992
    Abstract: In a mobile soil working device comprising a machine frame (23), a drive for at least one penetration tool (3) adapted for up and down movement, the penetration tool (3) being adapted to be driven into the soil and to be pulled out again, a guide element (4) for at least one penetration tool (3), the guide element being guided movably at the machine frame (23), a tool holder (2) for the penetration tool (3), which is supported for pivotal movement about a first pivot axis (40) in the guide element (4) movable up and down by the drive, so as to allow a pivoting of the penetration tool (3) against a spring force while the tool is in the soil, it is provided that, between the tool holder (2) and the guide element (4), a torsion element (1a, 1b, 1c) is provided coaxially with the first pivot axis (40), which torsion element, under a force effect on the at least one penetration tool (3), allows the tool holder (2) to pivot relative to the guide element (4) and, when the force effect ceases, exerts a restoring mome
    Type: Grant
    Filed: July 6, 2011
    Date of Patent: October 23, 2012
    Assignee: Redexim Handel-En Exploitatie Maatschappij B.V.
    Inventor: Cornelius Hermanus Maria de Bree
  • Patent number: 8293164
    Abstract: The present invention provides a molding die and a control method thereof aimed at shortening cycle time from heating to cooling of a molding cavity of the die with a simple and inexpensive configuration. In a molding die equipped with a molding cavity to mold a base material, a magnetic die material is used for the molding cavity, cooling means to feed a refrigerant is installed inside the molding cavity along a molding face and heating means by high-frequency induction is installed around the cooling means, and the molding cavity is alternately heated and cooled repeatedly by the heating means and the cooling means when the base material is molded with the molding cavity. Here, the cooling means includes a tubular body installed in the molding cavity, feeds a refrigerant when the molding cavity is cooled, and is in a hollow state of not containing the refrigerant when the molding cavity is heated.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: October 23, 2012
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Mitsuo Kusano, Kazuya Suzuki
  • Patent number: 8294510
    Abstract: There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyoo Itoh, Masanao Yamaoka
  • Patent number: 8288221
    Abstract: A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO2) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takahisa Eimori, Nobuyuki Mise
  • Patent number: 8286353
    Abstract: A method of manufacturing an outer retainer for a one-way clutch having an outward flange at one side edge thereof involves punching out a part of an annular portion having the outward flange by sliding a punch toward an axis of the outer retainer substantially in an axially inner direction from a retainer outer periphery-sided curve portion of the outward flange to a retainer inner periphery-sided curve portion thereof in a way that uses a die and the punch.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: October 16, 2012
    Assignee: NSK-Warner K.K.
    Inventors: Toshio Nagata, Hiroki Segawa, Hideki Oki, Seiji Nishimura
  • Patent number: 8289764
    Abstract: A highly-reliable, highly-integrated large-capacity phase-change memory is achieved. For this purpose, for example, memory tiles MT0, MT1 are provided respectively at points of intersection of global bit line GBL0 and global word lines GWL00B, GWL01B. Word lines WL000 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD0 which is controlled by GWL00B, and word lines WL001 of MT0, MT1 are commonly connected to an output from a word-line driving circuit WD1 controlled by GWL01B. For example, when WD0 is activated in accordance with a rewrite operation, an output from WD0 is connected to GBL0 via any one of four memory cells MC00, MC01 connected to WL000 of MT0, MT1.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: October 16, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Satoru Hanzawa
  • Patent number: 8288232
    Abstract: An improvement is provided in a manufacturing yield of a semiconductor device including transistors in which gate insulating films have different thicknesses. After a high-breakdown-voltage insulating film is formed over a silicon substrate, a surface of the high-breakdown-voltage insulating film is abraded for a reduction in the thickness thereof so that a middle-breakdown-voltage insulating film is formed to be adjacent to the high-breakdown-voltage insulating film. The high-breakdown-voltage insulating film is formed by a thermal oxidation method so as to extend from an inside of the main surface of the silicon substrate to an outside thereof. The middle-breakdown-voltage insulating film is formed so as to be thinner than the high-breakdown-voltage insulating film.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Fujii, Kazumasa Yonekura, Tatsunori Kaneoka
  • Patent number: 8291124
    Abstract: There is provided a semiconductor device having a reduced number of external terminals allocated for address input to receive access from outside, while realizing a high-speed response to an access from outside. The semiconductor device employs, in order to allow other external devices to directly access resources it possesses in its own address space, in an external interface circuit, external terminals which input a part of the address signal required for access from outside, a supplementary register which supplements the upper portion of address information that has been input from the external terminals, a mode register accessible from outside, and an address control circuit which generates an address signal to access the address space in a form based on information input from the external terminals, required supplementary information, and mode information of the mode register.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: October 16, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masaaki Hirano, Kunihiko Nishiyama
  • Patent number: 8284497
    Abstract: The present invention provides a zoom lens ZL comprising a first lens group G1 having positive refractive power, a second lens group G2 having negative refractive power, a third lens group G3 having positive refractive power, and a fourth lens group G4 having positive refractive power, the first lens group G1 including a negative meniscus lens L11 and a positive meniscus lens L12, the second lens group G2 including a negative meniscus lens L21, a biconcave negative lens L22 and a positive meniscus lens L23, and the fourth lens group G4 including one positive lens L41, and the refractive indexes of at least three lenses in the zoom lens ZL being greater than 1.9.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: October 9, 2012
    Assignee: Nikon Corporation
    Inventors: Norio Murayama, Sayako Yamamoto
  • Patent number: 8284582
    Abstract: The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 9, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazunari Inoue
  • Patent number: 8283210
    Abstract: Chip cracking that occurs when a dicing step using a blade is carried out to acquire semiconductor chips with the reduced thickness of a semiconductor wafer is suppressed. When the semiconductor wafer is cut at the dicing step for the semiconductor wafer, a blade is advanced as follows: in dicing in a first direction (Y-direction in FIG. 12) along a first straight line, the blade is advanced from a first point to a second point. The first point is positioned in a first portion and the second point is opposed to the first point with a second straight line running through the center point of the semiconductor wafer in between.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: October 9, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Nobuyasu Muto
  • Patent number: 8284481
    Abstract: An objective lens to be fitted into a fitting hole of a nosepiece of a microscope includes an imaging lens that is composed of a plurality of lens groups, and a lens barrel that holds the imaging lens. The lens barrel is formed with a fitting portion that is fitted to the fitting hole of the nosepiece and provided at an outer circumference of a tip portion side away by a given distance from the tip portion where a first lens group in the imaging lens is held, and a mount surface that comes into contact with a contact surface of the fitting hole of the nosepiece upon fitting at the fitting portion. The nosepiece is equipped with the objective lens. The inverted microscope is equipped with the nosepiece fitting the objective lens.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: October 9, 2012
    Assignee: Nikon Corporation
    Inventor: Takashi Kawahito
  • Patent number: 8278147
    Abstract: Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kado, Takahiro Naito, Toshihiko Sato, Hikaru Ikegami, Takafumi Kikuchi
  • Patent number: 8278708
    Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: October 2, 2012
    Assignees: Renesas Electronics Corporation, Hitachi Tobu Semiconductor Ltd.
    Inventors: Hiroshi Inagawa, Nobuo Machida, Kentaro Oishi
  • Patent number: 8280702
    Abstract: A computer system and method for determining a survivability aspect control signal for an aircraft is disclosed. The computer system can include a processor and a memory including software instructions adapted to cause the computer system to perform a series of steps. The steps can include providing a plurality of signature exposure models, each signature exposure model corresponding to a threat sensor and including a threat sensor characteristic and a threat operational characteristic. A portion of a mission can be selected along with one or more of the models based on the selected mission portion. The steps can include calculating a signature exposure index based on the one or more selected models and the selected mission portion and providing a survivability aspect control signal based on the signature exposure index.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 2, 2012
    Assignee: Lockheed Martin Corporation
    Inventor: Carl R. Herman
  • Patent number: 8278199
    Abstract: Reliability of a semiconductor element and its product yield are improved by reducing variations in the electrical characteristic of a metal silicide layer. After forming a nickel-platinum alloy film over a semiconductor substrate, by carrying out a first thermal treatment at a thermal treatment temperature of 210 to 310° C. using a heater heating device, the technique causes the nickel-platinum alloy film and silicon to react with each other to form a platinum-added nickel silicide layer in a (PtNi)2Si phase. After removing unreacted nickel-platinum alloy film, the technique carries out a second thermal treatment having the thermal treatment temperature higher than that of the first thermal treatment to form the platinum-added nickel silicide layer in a PtNiSi phase. The temperature rise rate of each thermal treatment is set to 10° C./s or more.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shigenari Okada, Takuya Futase, Yutaka Inaba
  • Patent number: 8281269
    Abstract: An object of the present invention is to largely reduce a period required for a layout design of a semiconductor integrated circuit device by simplifying a hierarchical layout process. It is necessary to couple a signal line between a circuit belonging to a top and a signal terminal of a block, and there is such an inadequate situation that the signal line cannot be coupled to a predetermined location of the signal terminal of the block or the signal line needs to be largely detoured depending on congestion conditions of the other signal lines in the block and the signal lines of the top coupled to the other blocks. Accordingly, location information of the signal terminal is deleted before the signal line is coupled, so that the signal line can be coupled irrespective of the location information of the signal terminal of the block.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Shibatani, Koki Tsurusaki
  • Patent number: D668890
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 16, 2012
    Assignee: Innovation U.S.A., Inc.
    Inventor: Per Weiss Andersen
  • Patent number: D668891
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: October 16, 2012
    Assignee: Innovation U.S.A., Inc.
    Inventor: Per Weiss Andersen
  • Patent number: RE43754
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: October 23, 2012
    Assignee: Innovation U.S.A., Inc.
    Inventor: Per Weiss Andersen