Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8315338
    Abstract: To detect phase mismatches between in-phase and quadrature signals of a quadrature demodulator. The phase mismatches can be detected using the signals obtained by removing high frequency components of output of a multiplier by a low pass filter, the output being the product of the in-phase signals of which low frequency components are removed by a first high pass filter by the quadrature signals of which low frequency components are removed by a second high pass filter.
    Type: Grant
    Filed: March 8, 2011
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Shigenori Hayase, Kazuyuki Hori
  • Patent number: 8314493
    Abstract: Bump electrodes (conductive members) bonded onto lands disposed at a peripheral portion side than terminals (bonding leads) electrically coupled to pads (electrode pads) of a microcomputer chip (semiconductor chip) are sealed with sealing resin (a sealing body). Thereafter, the sealing resin is ground (removed) partially such that a part of each of the bump electrodes is exposed. The step of protruding the part of each of the bump electrodes from a front surface of the sealing resin is performed, after the grinding step.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Kikuchi, Tomoaki Hashimoto, Tatsuya Hirai
  • Patent number: 8314032
    Abstract: A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tetsufumi Kawamura, Hiroyuki Uchiyama, Hironori Wakana, Mutsuko Hatano, Takeshi Sato
  • Patent number: 8310044
    Abstract: The heat-release properties of semiconductor device are to be improved and the reliability thereof is to be improved. The semiconductor device has a wiring substrate, a heat-releasing plate having a convex part inserted into a through-hole of the wiring substrate, a semiconductor chip mounted over the convex part of the heat-releasing plate, and a bonding wire coupling an electrode pad of the semiconductor chip with a bonding lead of the wiring substrate, and further has a sealing portion covering a portion of an upper surface of the wiring substrate, a sealing portion covering a portion of a lower surface of the wiring substrate including the semiconductor chip and the bonding wire, and a solder ball placed over a lower surface of the wiring substrate.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: November 13, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 8310753
    Abstract: A confocal scanning microscope including: an objective system (second objective lens 23 and objective lens 24) illuminating a sample SA with illumination light; a scanning mechanism 31 scanning the sample SA to obtain an intensity signal; and a scanning optical system 32 provided between the scanning mechanism and the objective system. The scanning optical system composed of, in order from the scanning mechanism side, a first positive lens group G1, a second negative lens group G2, and a third positive lens group G3. The third lens group has two chromatic aberration correction portions each formed by a positive lens and a negative lens or negative lens and positive lens. Glass materials are selected such that one performs chromatization and the other performs achromatization, thereby providing a confocal scanning microscope capable of correcting lateral chromatic aberration generated in the objective system in the specific wavelength region by the scanning optical system.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: November 13, 2012
    Assignee: Nikon Corporation
    Inventors: Fumio Suzuki, Naoshi Aikawa, Kotaro Yamaguchi
  • Patent number: 8305060
    Abstract: In a switching power source which controls a current which flows in an inductor through a switching element which performs a switching operation in response to a PWM signal, and forms an output voltage by a capacitor which is provided in series in the inductor, a booster circuit which is constituted of a bootstrap capacity and a MOSFET is provided between an output node of the switching element and a predetermined voltage terminal. The boosted voltage is used as an operational voltage of a driving circuit of the switching element, another source/drain region and a substrate gate are connected with each other such that when the MOSFET is made to assume an OFF state, and a junction diode between one source/drain region and the substrate gate is inversely directed with respect to the boosted voltage which is formed by the bootstrap capacity.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kyoichi Hosokawa, Ryotaro Kudo, Toshio Nagasawa, Koji Tateno
  • Patent number: 8305802
    Abstract: There is provided a technology which can allow a semiconductor chip formed with a nonvolatile memory to be sufficiently reduced in size. There is also provided a technology which can ensure the reliability of the nonvolatile memory. In a memory cell of the present invention, a boost gate electrode is formed over a control gate electrode via an insulating film. The boost gate electrode has the function of boosting a voltage applied to a memory gate electrode through capacitive coupling between the boost gate electrode and the memory gate electrode. That is, during a write operation or an erase operation to the memory cell, a high voltage is applied to the memory gate electrode and, to apply the high voltage to the memory gate electrode, the capacitive coupling using the boost gate electrode is subsidiarily used in the present invention.
    Type: Grant
    Filed: October 23, 2010
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshiyuki Kawashima, Takashi Hashimoto
  • Patent number: 8304820
    Abstract: Processing of memory cells forming a nonvolatile memory in a semiconductor device. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.
    Type: Grant
    Filed: November 24, 2011
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hideaki Yamakoshi, Hideyuki Yashima, Shinichiro Abe, Yasuhiro Taniguchi
  • Patent number: 8299822
    Abstract: A driver circuit transmits a signal generated by a signal level generation circuit to a circuit to be measured by transmitting the signal to a output buffer circuit via a circuit (prebuffer circuit) that drives the output buffer circuit and causing the output buffer circuit to drive a transmission line. The driver circuit includes the prebuffer circuit and a replica buffer circuit formed by imitating the prebuffer circuit. The prebuffer circuit and the replica buffer circuit are disposed in parallel. The driver circuit temporarily increases input bias current to be supplied to output-stage transistors of the output buffer circuit on the basis of output current of the replica buffer circuit during transition of an input or output signal.
    Type: Grant
    Filed: January 8, 2011
    Date of Patent: October 30, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yasuo Shima, Katsuya Sonoyama, Yoichiro Kobayashi
  • Patent number: 8298963
    Abstract: With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Minoru Kimura, Masao Odagiri
  • Patent number: 8298919
    Abstract: A method to prevent contamination of the principal surface side in a process of grinding the back surface side of a semiconductor wafer. At an intersection of a scribe region of a semiconductor wafer whose back surface side is to be ground, a plurality of insulating layers is laminated over the principal surface in the same manner as an insulating layer constituting a wiring layer laminated over a device region. Moreover, in the same layer as an uppermost wiring disposed at the uppermost layer among a plurality of the wiring layers formed for a device region, a metal pattern is formed. Furthermore, a second insulating layer covering the uppermost wiring is also formed over the metal pattern so as to cover the same.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shoetsu Kogawa, Satoru Nakayama, Seigo Kamata, Shigemitsu Seito
  • Patent number: 8299599
    Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Nakamura, Atsushi Fujiki, Tatsuhiro Seki, Nobuya Koike, Yukihiro Sato, Kisho Ashida
  • Patent number: 8299495
    Abstract: In a reverse conducting IGBT, diode cathode regions are formed dispersedly on the back side of a device chip. When the distribution density of the diode cathode region becomes low, VF of a fly-back diode, that is, a forward voltage drop becomes large. On the other hand, when the distribution density of the diode cathode region becomes high, it becomes hard for a PN junction at a collector part to turn ON and a snap back occurs. In contrast to this, there is a method of providing about one to several diode cathode absent regions having a macro area, however, the arrangement of the regions itself directly affects the device characteristics, and therefore, it is difficult to control the device characteristics and variations thereof.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Inagawa
  • Patent number: 8298317
    Abstract: A steelmaking process is disclosed. The process includes producing molten steel and molten steelmaking slag in a steelmaking process, the steelmaking slag including iron units and flux units, and thereafter producing molten iron in a molten bath based direct smelting process using a substantial portion of the steelmaking slag as part of the feed material requirements for the direct smelting process. A direct smelting process is also disclosed. The process includes pre-treating ferrous material including steelmaking slag and thereafter direct smelting molten iron using the pretreated ferrous material as part of the feed material for the process.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: October 30, 2012
    Assignee: Technological Resources Pty. Limited
    Inventors: Rodney James Dry, Robin John Batterham
  • Patent number: 8301915
    Abstract: The present invention enables a power-supply voltage terminal and an internal circuit to be isolated from each other in a noncontact operation without largely increasing a chip area in a semiconductor integrated circuit device for an IC card.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuki Watanabe, Nobuaki Yoneya
  • Patent number: 8299600
    Abstract: A semiconductor device is provided with improved reliability. A semiconductor chip is mounted over a chip mounting portion of a lead frame via solder. A metal plate is arranged over a source pad of the semiconductor chip and a lead portion of a lead frame via solder. A solder reflow process is performed thereby to bond the semiconductor chip over the chip mounting portion with a solder, and to bond the metal plate to the source pad and the lead portion with the other solders. The lead frame is formed of a copper alloy, and thus has its softening temperature higher than the temperature of the solder reflow process. The metal plate is formed of oxygen-free copper, and has its softening temperature lower than the temperature of the solder reflow process, whereby the metal plate is softened in the solder reflow process. Thereafter, a gate pad electrode of the semiconductor chip is coupled to a lead portion via the wire, a sealing resin portion is formed, and then the lead frame is cut.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yukihiro Sato, Katsuhiko Funatsu, Hiroyuki Nakamura
  • Patent number: 8300308
    Abstract: An eyepiece base unit and a microscope with which a phase contrast observation function can be easily added to the microscope. The eyepiece base unit is removably attached to a main unit of the microscope, and includes, in a state of being attached to the microscope, a pupil conjugate plane, which is a plane conjugate with an image side focal plane of an objective lens in an observation optical system of the microscope. By rotating a turret around a central axis, phase plates installed in the turret can be inserted into the pupil conjugate plane.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: October 30, 2012
    Assignee: Nikon Corporation
    Inventor: Masaaki Tamura
  • Patent number: 8294510
    Abstract: There is provided an output stage circuit including such MOSTs (M) that when their gates and sources are respectively set to an equal voltage, subthreshold leakage currents substantially flow between their drains and sources, wherein upon its deactivation, a voltage is applied to the gate of each of the MOSTs (M) in such a manner than a reverse bias is applied between the gate and source of the MOST (M). That is, when the MOST (M) is of a p channel type, a voltage higher than that of a p type source is applied to its gate. When the MOST (M) is of an n channel type, a voltage lower than that of an n type source is applied to its gate. Upon activation of the circuit, the MOST is held in a reverse bias state or controlled to a forward bias state according to an input voltage. A CMOS circuit and a semiconductor device can be realized each of which is small in leakage current even though its threshold voltage is low and which is operated at high speed and with a small voltage amplitude.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kiyoo Itoh, Masanao Yamaoka
  • Patent number: 8294186
    Abstract: A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshifumi Iwasaki, Yoshihiko Kusakabe
  • Patent number: 8293648
    Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: October 23, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Takuya Futase, Tomonori Saeki, Mieko Kashi