Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8323992
    Abstract: The variation in the contact pressures of the plurality of contact terminals to the plurality of chip electrodes is decreased. A thin-film sheet (first sheet) includes: a principal surface (contact-terminal formation surface) on which a plurality of contactors (contact terminals) are formed; and a rear surface positioned on an opposite side to the principal surface. Also, in the thin film sheet, a plurality of wirings and dummy wiring are arranged between the principal surface and the rear surface. A slit formed of an opening portion penetrating from the principal surface of the thin-film sheet to the rear surface thereof is formed along the wiring between the dummy wiring and the contactor arranged at an end of a contactor group (first contact terminal group) in which the plurality of contactors are aligned.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Seigo Nakamura, Iwao Natori, Yasuhiro Motoyama
  • Patent number: 8327180
    Abstract: A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface with an external device such as a memory card, the interface unit is provided with an output driver connected to an external terminal for outputting a clock signal to output the clock signal and with an equivalent load circuit capable of imparting, to the clock signal extracted from an arbitrary position in a stage previous to the output driver in a clock signal path, delay equivalent to delay resulting from an external load connected to the external terminal in order to generate a clock signal for latching data inputted from the memory card.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuo Sakamoto, Naozumi Morino, Ikuo Kudo
  • Patent number: 8325128
    Abstract: In a display device such as a liquid crystal display, a processing for compressing a range of display data (grayscale) to a low grayscale side (a grayscale range where response is fast) except for a high grayscale side (a grayscale range where response is slow) at a predetermined compression ratio to conduct display according to response characteristic of transition between grayscales and a temperature state and a processing for increasing a light amount of a backlight to compensate for luminance change due to the compression are performed, for example, in a liquid crystal panel of TN liquid crystal. Thereby, response can be made fast even at a low temperature time.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yukari Katayama, Yoshiki Kurokawa, Akihito Akai, Goro Sakamaki
  • Patent number: 8324092
    Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kan Yasui, Digh Hisamoto, Tetsuya Ishimaru, Shin-Ichiro Kimura
  • Patent number: 8325524
    Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
  • Patent number: 8323555
    Abstract: A container forming assembly and method includes receiving a parison within a cavity of a mold, enclosing the parison within the mold having a wall with a recess, inflating the parison in the mold to form a blow molded container where the blow molded container has a sidewall, a movable region formed at the recess, and a hinge circumscribing an interface between the sidewall and the movable region, and moving the movable region toward an interior of the blow molded container about the hinge before filling. Furthermore, a method for forming a container includes receiving a parison, enclosing the parison with a mold that includes a cavity, and inflating the parison in said mold to form a blow molded container with a moveable region at the cavity. The method further includes repositioning the moveable region before filling the blow molded container.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: December 4, 2012
    Assignee: Graham Packaging Company L.P.
    Inventors: Gregory Trude, Paul Kelley
  • Patent number: 8324706
    Abstract: A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Keiichi Yoshizumi, Kazuhisa Higuchi, Takayuki Nakaji, Masami Koketsu, Hideki Yasuoka
  • Patent number: 8319345
    Abstract: A semiconductor packaging substrate with a plurality of pads arranged in a square grid pattern thereon, in which among the pads, two pads obliquely adjacent to each other are connected with through-holes respectively and another through-hole is provided between the through-holes connected with the two pads obliquely adjacent to each other.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tatsunobu Abe, Seiji Miyamoto
  • Patent number: 8319352
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: June 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Patent number: 8319874
    Abstract: Suppressing a fall in sensitivity upon shooting without causing similar effect as a pixel defect in spite of being able to perform focal point detection. When a gate electrode 67 is high, pinned photodiodes 41, 42 are electrically connected with each other. At this moment, a lower area of the gate electrode 67 has a photoelectric conversion function. On the other hand, when the gate electrode 67 is low, pinned photodiodes 41, 42 are electrically separated with each other. At this moment, the lower area of the gate electrode 67 does not have any photoelectric conversion function.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: November 27, 2012
    Assignee: Nikon Corporation
    Inventor: Satoshi Suzuki
  • Patent number: 8317161
    Abstract: An air balancer has a rotary drum on which a rope member is to be wound and that is supported rotatably by a stationary shaft in a casing, a conversion system that converts pressure of first air supplied into the casing into rotational force of the rotary drum for winding the rope member on the rotary drum, a rotary member that is rotatably supported by the stationary shaft and linked with the rotary drum to integrally rotate therewith, a rotation restriction member to be in contact with the rotary member to restrict rotation thereof, a disengagement mechanism that causes the rotation restriction member to retract by pressure of second air supplied into the casing to thereby disengage the contact between the rotary member and the rotation restriction member, and a control module having an air circuit that supplies the second air into the casing only when the first air is supplied into the casing or when the first air is discharged from the casing.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: November 27, 2012
    Assignee: Endo Kogyo Co., Ltd.
    Inventor: Nobuaki Fujii
  • Patent number: 8319274
    Abstract: A gate dielectric functioning as a charge-trapping layer of a non-volatile memory cell with a structure of an insulator gate field effect transistor is formed by laminating a first insulator formed of a silicon oxide film, a second insulator formed of a silicon nitride film, a third insulator formed of a silicon nitride film containing oxygen, and a fourth insulator formed of a silicon oxide film in this order on a main surface of a semiconductor substrate. Holes are injected into the charge-trapping layer from a gate electrode side. Accordingly, since the operations can be achieved without the penetration of the holes through the interface in contact to the channel and the first insulator, the deterioration in rewriting endurance and the charge-trapping characteristics due to the deterioration of the first insulator does not occur, and highly efficient rewriting (writing and erasing) characteristics and stable charge-trapping characteristics can be achieved.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Digh Hisamoto, Itaru Yanagi, Yasuhiro Shimamoto, Toshiyuki Mine, Yutaka Okuyama
  • Patent number: 8319705
    Abstract: The plasma display device has a display panel having first and second display electrodes and address electrodes, an electrode drive circuit, and a drive control circuit for controlling the electrode drive circuit. The drive control circuit performs a reset drive control, address drive control and sustain drive control in each subfield. The drive control circuit performs an all cell reset drive control which resets all cells in a first subfield out of the plurality of subfields, and an ON cell reset drive control which resets ON cells in a second subfield. At a first temperature T1, an ultimate potential of an slope pulse of the first display electrode is controlled to be a first potential in the ON cell reset drive control, and at a second temperature T2>T1, the ultimate potential is controlled to be a second potential higher than the first potential.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: November 27, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Junichi Kumagai, Katsumi Ito
  • Patent number: 8316613
    Abstract: A shrapnel containment system is provided which is adapted to be installed at an interior of a building wall to contain shrapnel from a blast, the system including a panel made of a layer of elastomeric material and fastener elements to fasten the layer to a wall of a structure, with the panel optionally including a fabric reinforcing layer. A method for producing the panel is also provided.
    Type: Grant
    Filed: April 6, 2004
    Date of Patent: November 27, 2012
    Assignee: Life Shield Engineered Systems, LLC
    Inventor: Bruce S. Hall
  • Patent number: 8320222
    Abstract: The present invention enables a comprehensive evaluation from both of data read from a disk and a servo signal of a servo controller. The present invention provides a semiconductor integrated circuit mountable to a disk recording and reproducing drive, which comprises a signal processor of an RF signal read from a pickup, a servo controller responsive to a servo error signal read from the pickup, a memory controller, and an external interface. The memory controller is supplied with read data and a servo signal and stores the read data and the servo signal in a buffer memory according to a time division process. The read data and the servo signal stored in the buffer memory can be transferred to an external device via the external interface by the memory controller.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Norihiko Nakano, Hajime Ishihara, Akio Fukushima
  • Patent number: 8319328
    Abstract: Chipping of semiconductor chips is to be prevented. A semiconductor device comprises a semiconductor chip having a main surface, a plurality of pads formed over the main surface, a rearrangement wiring formed over the main surface to alter an arrangement of the plurality of pads, and a protective film and an insulating film formed over the main surface, and a plurality of solder bumps each connected to the rearrangement wiring and arranged differently from the plurality of pads. The presence of a bevel cut surface obliquely continuous to the main surface and formed on a periphery of the main surface of the semiconductor chip prevents chipping.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Noriyuki Takahashi
  • Patent number: 8321687
    Abstract: A cryptographic system with a modular architecture. Memory modules make it possible to store information concerning authentication keys, data and commands, including a secure memory module for containing the keys with integrity checking and an emergency erase function. Various types of algorithm modules perform cryptographic functions of the cryptographic system by executing the commands stored in at least one memory module. External interface modules are utilized that make it possible to produce the link between the cryptographic system and external devices, through a standard or proprietary input/output bus. A control unit is responsible for the supervision of the various algorithm modules and the management of the keys, and a central interconnect module assures handling of secure exchanges between blocks.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: November 27, 2012
    Assignee: BULL S.A.S.
    Inventor: Patrick LeQuere
  • Patent number: 8313969
    Abstract: The present invention comprises a method for preparing a nanocrystal having (i) a core comprising a semiconductor comprising A representing a metal or metalloid in the +III oxidation state and B representing an element in the ?III oxidation state, coated with (ii) a shell in which the outer portion comprises a semiconductor having the formula ZnS1-xEx, where E represents an element in the ?II oxidation state and x is a decimal number such that 0?x<1, said method comprising a step consisting of heating a mixture of at least one precursor of A, at least one precursor of B, at least one precursor of zinc, at least one precursor of sulphur and, optionally, at least one precursor of E, from a temperature T1 to a temperature T2 greater than T1 in an increasing manner and so as to form, firstly, said core then said shell. The present invention also concerns a nanocrystal obtainable by the invention method and uses thereof.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 20, 2012
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Peter Reiss, Li Liang
  • Patent number: 8314502
    Abstract: To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P1a is formed in the same layer as that of a second layer wiring and the pattern P1b is formed in the same layer as that of a first layer wiring. Further, the pattern P2 is formed in the same layer as that of a gate electrode, and the pattern P3 is formed in the same layer as that of an element isolation region.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masami Koketsu, Toshiaki Sawada
  • Patent number: 8316217
    Abstract: A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface to be used in big endian or little endian mode. The first register holds control data of the switching circuit. The switching circuit sets the interface in little endian mode when first predetermined control information is supplied to the first register, and sets the interface in big endian mode when second predetermined control information is supplied to the first register. The control information can be correctly inputted without being influenced by the endian setting status.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: November 20, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Goro Sakamaki, Yuri Azuma