Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8209267
    Abstract: A method for performing automatic account adjustment including performing automatic account adjustment processing on an account associated with a source of a unique postal indicium, if scanned information about the unique postal indicium indicates an incorrect tariff associated with a mail piece to which the unique postal indicium is affixed. The method may also include outputting information to report results of the automatic account adjustment processing, if scanned information about the unique postal indicium indicates an incorrect tariff associated with a mail piece to which the unique postal indicium is affixed.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: June 26, 2012
    Assignee: Lockheed Martin Corporation
    Inventor: Jeffrey S. Poulin
  • Patent number: 8208202
    Abstract: A focus detection apparatus is provided with a light source 16 that emanates light with a given wavelength range; a reflection member 15 that reflects light emanated from the light source 16 to lead to an object 6a, reflects light from the light source 16 reflected from the object 6a, and transmits light from the object 6a with at least two different wavelength ranges except the light reflected from the object 6a; a photodetector 21 detecting the light from the light source 16 reflected from the object 6a; and a controller 22 detecting a focus shift between the objective lens 8 and the object 6a in the microscope 2 based on a signal detected by the photodetector 21, thereby providing a focus detection apparatus capable of limiting wavelength range of light for focus detection thereby able to use wider wavelength range for the microscope observation, and a microscope equipped therewith.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: June 26, 2012
    Assignee: Nikon Corporation
    Inventor: Ichiro Sase
  • Patent number: 8206997
    Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: June 26, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura, Kenji Kawakami
  • Patent number: 8202420
    Abstract: A method and device for blood treatments that use fluids such as dialysate and replacement fluid for renal replacement therapy. In an embodiment, fluid is passed either by pump or passively by gravity feed, through a microporous sterilization filter from a fluid source to a replacement fluid container. The latter forms a batch that may be used during treatment. The advantage of forming the batch before treatment is that the rate of filtering needn't match the rate of consumption during treatment. As a result, the sterilization filter can have a small capacity. In another embodiment, a filter is placed immediately prior to the point at which the sterile fluid is consumed by the treatment process. The latter may be used in combination with the former embodiment as a last-chance guarantee of sterility and/or that the fluid is free of air bubbles. It may also be used as the primary means of sterile-filtration.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: June 19, 2012
    Assignee: NxStage Medical, Inc.
    Inventors: James M. Brugger, Jeffrey H. Burbank, Brian C. Green
  • Patent number: 8203210
    Abstract: The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Furusawa, Takao Kamoshima, Masatsugu Amishiro, Naohito Suzumura, Shoichi Fukui, Masakazu Okada
  • Patent number: 8202740
    Abstract: A semiconductor device for SiP or PoP for downsizing, a method of manufacturing it, and a testing method suitable for SIP and PoP in which the simplification of a system and the enhancement of its efficiency are achieved are provided. A first semiconductor device including a first memory circuit determined as non-defective and a second semiconductor device including a second memory circuit and a signal processing circuit carrying out signal processing according to a program, determined as non-defective are sorted. The sorted devices are assembled as an integral semiconductor device. On a board for testing, a clock signal equivalent to the actual operation of the semiconductor device is supplied. A test program for conducting a performance test on the first memory circuit is written from a tester to the second memory circuit of the second semiconductor device.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kanya Hamada, Tasuke Tanaka, Akira Seito, Yoshiaki Nakajima
  • Patent number: 8203868
    Abstract: An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode. Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area. Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masanao Yamaoka, Takayuki Kawahara
  • Patent number: 8200878
    Abstract: The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip.
    Type: Grant
    Filed: January 8, 2008
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Koichi Ishimi
  • Patent number: 8200934
    Abstract: To reduce overhead of data transfer between processor cores and improve a processing capability of a processor, there is provided a processor including: a CPU for performing computing processing; an internal memory for storing data; and a data transfer unit for performing data transfer between the internal memory and a shared memory, in which: the data transfer unit includes: a command chain module for executing a command sequence formed of a plurality of commands including a data transfer instruction; and a monitor module for reading data set in advance in the internal memory and repeatedly monitoring the data until a comparative value and a value of the data become equal to each other, when one of the plurality of commands of the command sequence thus read is a predetermined command; and the command chain module executes a next command in the command sequence after the monitor module has finished monitoring.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: June 12, 2012
    Assignees: Hitachi, Ltd., Renesas Electronics Corporation, Waseda University
    Inventors: Hironori Kasahara, Keiji Kimura, Takashi Todaka, Tatsuya Kamei, Toshihiro Hattori
  • Patent number: 8198162
    Abstract: Provided is a manufacturing method of a semiconductor device wherein the generation of voids is prevented in aluminum-based electrodes or the like. The method is suitable for manufacturing a semiconductor device adapted for vehicles, which is required to have a high reliability. However, it is very difficult that power semiconductor devices such as power MOSFETs, in particular, trench gate type power MOS devices are formed without having any void since the thickness of aluminum-based electrodes thereof is as large as about 3500 to 5500 nm (2.5 ?m or more). In the present invention, a method is provided wherein at the time of forming an aluminum-based electrode metal film positioned over a wafer and having a thickness of 2.5 ?m or more over a highland/lowland-repeated region in a line and space form by sputtering, the temperature of the wafer is set to 400° C. or higher and lower than 500° C.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuya Sekiguchi, Yoshio Fukayama, Yuji Takahashi, Tomokuni Chino, Tsuyoshi Kachi, Katsuhiro Mitsui, Daisuke Ono, Tatsuhiko Miura
  • Patent number: 8200152
    Abstract: There is provided a semiconductor integrated circuit provided with a charge pump circuit of low power consumption, capable of maintaining an output voltage thereof at a predetermined voltage level without causing current consumption to undergo intermittent variation, and a contactless electronic device using the semiconductor integrated circuit. With respective charge pump circuit unit cells (charge/discharge circuits) making up the charge pump circuit, charge current/discharge current flowing to or from the capacitor, respectively, is controlled according to the output voltage of the charge pump circuit. Accordingly, the charge pump circuit can maintain the output voltage thereof at the predetermined voltage level without undergoing an intermittent action.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kazuki Watanabe
  • Patent number: 8198983
    Abstract: Depending on the power supplied to the non-contact electronic device, the voltage suppression characteristic of the regulator function mounted in a power supply circuit is changed. When the power supplied to the non-contact electronic device is small, the voltage change amount of the voltage between antenna terminals for the current flowing in the antenna is increased, and when the power supplied to the non-contact electronic device is large, the voltage change amount of the voltage between the antenna terminals for the current flowing in the antenna is decreased. By this means, the current change of the entire consumption current for the current change of the load modulator (transmitting circuit) at the time of the long distance communication is increased.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuki Watanabe, Hisataka Tsunoda, Tetsuo Funane
  • Patent number: 8199549
    Abstract: The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data.
    Type: Grant
    Filed: August 19, 2010
    Date of Patent: June 12, 2012
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
  • Patent number: 8198698
    Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Maeda, Yasushi Sekine, Tetsuya Watanabe
  • Patent number: 8199415
    Abstract: A zoom lens system comprises, in order from an object, a first lens group having a positive refractive power, a second lens group having a negative refractive power, and a third lens group having a positive refractive power. The first lens group has a first-a partial lens group and a first-b partial lens group arranged on an image side of the first-a partial lens group with an air space and is constructed such that the first-b partial lens group moves along an optical axis direction upon focusing from infinity to a close-range object. The third lens group is constituted by a third-a partial lens group having a positive refractive power and a third-b partial lens group having a negative refractive power arranged on the image side of the third-a partial lens group with an air space.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: June 12, 2012
    Assignee: Nikon Corporation
    Inventor: Toshinori Take
  • Patent number: 8199411
    Abstract: An imaging lens SL installed in an SLR camera includes a front group disposed to the most object side and having negative power, and a rear group disposed to an image side of the front group and having negative power. At least a portion of the rear group is movable perpendicularly to an optical axis. The rear group includes a first negative component having negative power, a second negative component having negative power, and a positive component having positive power. The second negative component is disposed between the first negative component and the positive component. The second negative component side surface of the first negative component faces the second negative component, and the second negative component having a negative meniscus shape with a concave surface facing the first negative component. Thereby providing an imaging lens having excellent optical performance, an optical apparatus equipped therewith, and a method for manufacturing thereof.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: June 12, 2012
    Assignee: Nikon Corporation
    Inventor: Makoto Fujimoto
  • Patent number: 8199858
    Abstract: The present invention provides an OOB detection circuit capable of making accurate signal determination even in the case where a characteristic fluctuation occurs in an analog circuit, thereby preventing deterioration in the yield of a product. To an amplitude determining circuit, a characteristic adjustment register for changing setting of an amplitude threshold adjustment mechanism for distinguishing a burst and a squelch from each other provided for the amplitude determining circuit is coupled. The characteristic adjustment register is controlled by a self determination circuit. An output of the amplitude determination circuit is supplied to a time determining circuit and also to the self determination circuit. On the basis of the output of the amplitude determining circuit, the self determination circuit controls the characteristic adjustment register.
    Type: Grant
    Filed: December 6, 2008
    Date of Patent: June 12, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuaki Kurooka, Kenichi Shimizu
  • Patent number: 8199596
    Abstract: A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: June 12, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Akiyama, Riichiro Takemura, Takayuki Kawahara, Tomonori Sekiguchi
  • Patent number: 8192387
    Abstract: Blood treatment system and method for high rate hemofiltration ensures against pyrogenic patient reaction by providing various mechanisms for filtering replacement fluid to remove endotoxins and other safety features including detecting incorrect fluid administration.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: June 5, 2012
    Assignee: NxStage Medical, Inc.
    Inventors: James M. Brugger, Jeffrey H. Burbank
  • Patent number: 8193053
    Abstract: An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times. In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: June 5, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Digh Hisamoto, Shin'ichiro Kimura, Daiske Okada, Kan Yasui