Abstract: Providing a pair of binoculars that is able to prevent diopter from being changed after adjusting diopter difference by pushing down the focus knob after adjusting diopter difference so as not to touch the operating knob, and able to prevent the focus position from being changed after adjusting focus position by pulling out the focus knob to create a focus lock state after adjusting focus position.

Abstract: A telescope optical system TL comprising, in order from an object side: an objective lens 1; an erecting prism 2; and an eyepiece 3; the objective lens 1 comprising, in order from the object side, a first lens group G1 having positive refractive power, a second lens group G2 having negative refractive power, and a third lens group G3 having positive refractive power, focusing being carried out by moving the second lens group G2 along an optical axis, and an image position being movable by moving the third lens group G3 in a direction perpendicular to the optical axis, thereby providing a telescope optical system having optimum optical performance for a telescope.

Abstract: A small shooting lens has high optical performance and is suitable for mass production. To attain this, the shooting lens includes at least three lens groups disposed in order from an object side, wherein an adhesion multiple-layer diffractive optical element is formed on one of surfaces disposed between an object surface and an imaging plane, and a maximum image height Y and an entire length L satisfy 0.1<Y/L<3.0 . . . (1). Thus using the multiple-layer diffractive optical element in the shooting lens makes it possible to improve diffraction efficiency over a wide range and reduce flare. Particularly, the multiple-layer diffractive optical element has a merit that its production and assembling are easy. Further, according to the conditional expression (1), it is possible to realize the downsizing of the shooting lens while also maintaining its imaging quality.

Abstract: The yield of a semiconductor device is improved. Inside the resin sealing body which forms a semiconductor device, the semiconductor chip is sealed in the state where it has arranged aslant to the upper and lower sides of a resin sealing body. In the suspension lead which supports the die pad carrying this semiconductor chip, the small recess is formed in the fifth surface of the opposite side with the surface on which the semiconductor chip was mounted. This recess is a portion used as the starting point when making die pad 2a slanting. The side surface of the side near a die pad between two side surfaces of this recess is formed in the state where it inclined rather than the side surface of the side near the periphery of a resin sealing body.

Abstract: Input data (1A) having an integral multiple of 8 bits is divided into symbols in units of b bits (b is an integer of 5 to 7) in a register file 10, an error detecting code is added in an error detection calculation circuit 20, and then encoding (such as Reed Solomon (RS) encoding) having an error correction capability of two or more symbols is performed in a parity calculation circuit 30 to record the data in a storage 40. In the reproduction, error correction in units of symbols is performed to reproduced data from the storage 40 in an error correction circuit 70, error detection processing is performed in an error detection calculation circuit 80, and then data having the integral multiple of 8 bits is recovered in a register file 90 to output the same. By this means, it is possible to provide a storage system with high reliability to a soft error that occurs in a storage such as semiconductor memory.

Abstract: A power supply circuit includes first and second switching MOSFETS. A semiconductor device, including the second switching MOSFET, has a plurality of transistor cell regions disposed in a semiconductor substrate. A source electrode of the second MOSFET is disposed over a main surface of the semiconductor substrate and is in contact with a top surface of a source region in each of the plurality of transistor cell regions. A drain electrode of the second MOSFET is disposed over a back surface of the semiconductor substrate and is electrically connected to the semiconductor substrate. A Schottky cell region is disposed between the plurality of transistor cell regions in the semiconductor substrate. The source electrode is in contact with a part of the main surface of the semiconductor so as to form a Schottky junction in the Schottky cell region.

Abstract: The reliability of a photosensor-type semiconductor device is enhanced. The sealing step in a manufacturing process for the semiconductor device is carried out as described below. A molding die having an upper die and a lower die is prepared and a film is arranged between the upper die and the lower die. A lead frame in which first adhesive, a semiconductor chip, second adhesive 11, and a base material are mounted over the upper surface of each tab is arranged between the film and the lower die. The base material has an opening formed therein and the opening is covered with a protective sheet. The semiconductor chip has a light receiving area formed in its main surface. The upper die and the lower die are clamped to cause part of the base material to bite into the film. Thereafter, sealing resin is supplied to between the film and the lower die to form a blanket sealing body. Thus the photosensor-type semiconductor device without resin flash over the light receiving area is obtained.

Abstract: A Cu-CMP step applied to processes for 130 nm, 90 nm, and 65 nm technical nodes or the like mainly employs slurry to which an anticorrosive agent is added for preventing corrosion of Cu wiring. The inventors of the present application have studied and clearly found that in the Cu-CMP step using the slurry with the anticorrosive agent added thereto, the anticorrosive agent often forms complexes with Cu, which remain as foreign matter on a wafer in large quantity, leading to a reduction in yield, and in reliability of TDDB characteristics of the Cu wiring. In the invention of the present application, a post-CMP cleaning process involves applying wet cleaning to a wafer by supplying a cleaning solution, such as a chemical solution or pure water, to a device surface of the wafer substantially in a vertical direction with respect to the horizontal device surface, while rotating the wafer substantially about its center in the horizontal plane.

Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.

Abstract: A confocal microscope apparatus is capable of obtaining a high confocal effect while detecting an image of a specimen line by line. The confocal microscope apparatus may include an illuminating optical system which illuminates a line-shaped area on a specimen plane in a specimen by collected light, an image-forming optical system which forms an image of light emitted from the specimen plane, a two-dimensional light detector which is placed at a conjugate plane of the specimen plane, a scanning unit which moves the line-shaped area on the specimen plane, and a correcting unit which corrects a pixel signal of a specific line on the two-dimensional light detector having a confocal relation with the line-shaped area based on a pixel signal of a peripheral line of the specific line.

Abstract: There is provided a semiconductor device that enables high-speed data read and reduces the area of a drive circuit for activating a word line. By signal transmission through a common word line having a low resistance and coupled at a plurality of points to a word line, it is possible to read data at high speed. Further, since the common word line is provided common to a plurality of memory blocks, a word line driver can be provided common to the memory blocks. Further, by disposing a latch circuit, corresponding to a sub-digit line, for holding the active state of the common word line, it is possible to transmit a row selection signal during data write through the common word line and thereby reduce a metal wiring layer.

Abstract: Composing a zoom optical system ZL, in order from an object side, a first lens group G1 having positive refractive power, a second lens group G2 having negative refractive power, a third lens group G3 having positive refractive power, a fourth lens group G4 having positive refractive power, and a fifth lens group G5 having negative refractive power; and disposing each lens group with satisfying a given conditional expression (1); thereby providing a zoom optical system ZL capable of suppressing variation in aberrations upon zooming and carrying out excellent vibration reduction, an optical apparatus equipped therewith, and a method for manufacturing the zoom optical system.

Abstract: To reduce a processing load of an external CPU, when a large amount of data is initially set frequently to an image coding/decoding device. The image encoding/decoding device (data processing device) includes a first circuit and a second circuit for providing initial setting to a plurality of image processing modules (processor units), wherein the image encoding/decoding device does not receive information, which is initially set to the image processing modules, directly from the external CPU, and control information for the initial setting is set to the first circuit from the CPU. The second circuit reads in initial setting information and setting-target information of the initial setting information from outside using the control information set in the first circuit and transfers the initial setting information to the image processing module according to the read-in setting-target information.

Abstract: To improve the heat dissipation characteristics of a semiconductor device. The semiconductor device has a die pad, a heat dissipating plate in the form of a frame arranged between the die pad and a plurality of leads so as to surround the die pad, a plurality of members that connect the die pad and the inner edge of the heat dissipating plate, and a suspension lead linked to the outer extension of the heat dissipating plate, wherein a semiconductor chip the outer shape of which is larger than the die pad is mounted over the die pad and the members. The top surface of the die pad and the top surface of the members at the part in opposition to the back surface of the semiconductor chip are bonded to the back surface of the semiconductor chip in their entire surfaces with a silver paste.

Abstract: A computer system and method for identifying and pairing devices. The system includes a plurality of remote user interface computers, each having a display device and a user input device and each connected to a first network via a first respective data communication link. The system also includes a plurality of medical devices each having a medical device user interface and a second data communication link adapted to exchange data with the remote user interface computers. The system also includes a database adapted to communicate with the remote user interface computers via a connection to the first network or via a direct connection to one of the remote user interface computers, the database being adapted to store patient medical information including a treatment prescription that includes use of one of the medical devices.

Abstract: A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

Abstract: A semiconductor device includes plural electrode pads arranged in an active region of a semiconductor chip, and wiring layers provided below the plural electrode pads wherein occupation rates of wirings arranged within the regions of the electrode pads are, respectively, made uniform for every wiring layer. To this end, in a region where an occupation rate of wiring is smaller than those in other regions, a dummy wiring is provided. On the contrary, when the occupation rate of wiring is larger than in other regions, slits are formed in the wiring to control the wiring occupation rate. In the respective wirings layers, the shapes, sizes and intervals of wirings below the respective electrode pads are made similar or equal to one another.

Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].

Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.