Abstract: A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.

Abstract: A semiconductor device manufacturing technique which allows reduction of semiconductor chip size. First, a pad and other wires are formed over an insulating film. A surface protective film is formed over the insulating film including the pad and wires, and an opening is made in the surface protective film. The opening lies over the pad and exposes a surface of the pad. A bump electrode is formed over the surface protective film including the opening. Here, the pad is smaller than the bump electrode. Consequently, the wires are arranged just beneath the bump electrode in the same layer as the pad 10. In other words, the wires are arranged in space which becomes available because the pad is small enough.

Abstract: A technique permitting reduction in size of a standard cell is provided. In a semiconductor integrated circuit device comprising a first tap formed in a first direction to supply a power-supply potential, a second tap formed in the first direction to supply a power-supply potential and positioned so as to confront the first tap in a second direction intersecting the first direction, and a standard cell formed between the first and second taps, a cell height (distance) between the center of the first tap and that of the second tap both in the second direction is set to ((an integer+0.5)×a wiring pitch of the second-layer wiring lines) or [(an integer+0.25)×a wiring pitch of the second-layer wiring lines].

Abstract: There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip.

Abstract: A memory system including ROM and RAM in which reading and writing are enabled. A memory system includes a non-volatile memory (FLASH), DRAM, a control circuit, and an information processing device. Data in FLASH is transferred to SRAM or DRAM in advance. Data transfer between the non-volatile memory and the DRAM can be performed in the background. The memory system including these plural chips is configured as a memory system module in which each chip is mutually laminated and each chip is wired via a ball grid array (BGA) and bonding wire between the chips. Data in FLASH can be read at the similar speed to that of DRAM by securing a region in which the data in FLASH can be copied in DRAM and transferring the data to DRAM in advance immediately after power is turned on or by a load instruction.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: An exposure apparatus (EX) includes a setting apparatus (45) that sets an irradiation region (AR) of exposure light (EL) in a first state in which the irradiation light (EL) is irradiated onto a substrate (P) and irradiates, in a second state in which the exposure light (EL) is not irradiated onto the substrate (P), the exposure light (EL) onto a second region, which is different from a first region through which the exposure light (EL) passes in the first state, of a first surface of an optical member (FL) that is contacted with a liquid (LQ), to clean the second region by photochemical action.

Abstract: An easy open end for a pressurized food container, having an end panel and a conventional aperture score, surrounding the periphery of an aperture through which the contents of the container may be dispensed. A tab is provided to facilitate easy opening of the aperture. The easy open end also includes a vent score, which is arranged to rupture before the main aperture score, to vent the internal pressure in the container, before the container is opened. The end panel and/or tab also defines a shield to prevent the egress of product from the vent opening, when the vent score is severed.

Abstract: A technique capable of manufacturing a semiconductor device without posing contamination in a manufacturing apparatus regarding a phase change memory including a memory cell array formed of memory cells using a storage element (RE) by a variable resistor and a select transistor (CT). A buffer cell is arranged between a sense amplifier (SA) and a memory cell array (MCA) and between a word driver (WDB) and the memory cell array. The buffer cell is formed of the resistive storage element (RE) and the select transistor (CT) same as those of the memory cell. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.

Abstract: A semiconductor wafer inspection device which identifies an operator when an operation is performed and checks if the requested operation is permitted is provided. In a device that has already performed an operator authentication, the operator identification is further carried out when a particular operation is requested. If the operation requested is a permitted one, it is executed even if requested by an operator different from the one previously authenticated. The history of operations and the change history of in-device data are recorded and displayed. The operator authentication is performed only when necessary.

Abstract: A resistor R1 formed by forming a first resistor layer 5a of 20 nm thickness including a tantalum nitride film at a concentration of nitrogen of less than 30 at % and a second resistor layer of 5 nm thickness including a tantalum nitride film at a concentration of nitrogen of 30 at % or more successively by a reactive DC sputtering method using tantalum as a sputtering target material and using a gas mixture of argon and nitrogen as a sputtering gas, and then fabricating the first and the second resistor layers, in which the resistance change ratio of the resistor can be suppressed to less than 1% even when a thermal load is applied in the interconnection step, by the provision of the upper region at a concentration of nitrogen of 30 at % or more.

Abstract: Method and system for handling a plurality of hot-filled and capped containers having temporary deformations or distortions caused by vacuums induced in the containers. For each container, temporary deformations are confined or directed to a particular portion of the container. Annular hoop rings can be provided to confine the temporary deformations to a smooth sidewall portion of the container between the annular hoop rings. Alternatively, one or more supplemental vacuum panels can be provided to confine or direct the temporary deformation thereto. The annular hoop rings and the one or more supplemental vacuum panels can provide for substantially stable touch points for the container. The containers are conveyed with temporary deformations such that substantially stable contact points of each container are in contact with corresponding substantially stable contact points of other containers.

Abstract: This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.

Abstract: A continuous, non-metallic conduit for conductors, such as electrical wiring and/or fiber optic cable. The continuous conduit being formed from at least one pair of first and second conduits having enlarged ends coupled together. The enlarged ends are belled or otherwise have a diameter greater than that of the straight run (non-belled) portions of the conduit. The enlarged ends of the conduit being coupled together by fusion or welding, and an internal bead or ridge being formed by the coupling process. The enlarged ends are dimensioned such that the internal bead or ridge formed at the junction between the two enlarged ends does not project radially inward to a position equal to or less than the diameter of the straight run portion of the conduits. The continuous conduit is configured to allow the conductor to be passed therethrough such that the conductor does not contact the internal bead or ridge.

Abstract: There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Abstract: After the LEDs 2 (red LEDs (R), green LEDs (G) and blue LEDs (B), or white LEDs (W)) are mounted on the frame 3, without dicing the frame 3 for dividing the LEDs 2 into pieces, the tie bar is punched off to form an electric circuit. Thus, the RGB three primary color LED light source 1A or the white LED light source 1B that emits light in the state of the frame 3 can be manufactured.

Abstract: The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated.

Abstract: In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Abstract: A projection system includes: a projection device mounted at a member that moves through space and projects an optical image; a detection device that detects relative position assumed in the space by a projection target surface onto which the optical image is projected and the projection device; and a control device that controls projection by the projection device in correspondence to the relative position detected by the detection device.

Abstract: An apparatus, method and recording medium for controlling a game where a battle occurs in virtual space between one or more player characters acting according to manipulation of a player and one or more enemy characters acting independently of the manipulation of the player, including a command information storage for storing command information sets which includes a command to a player character and a plurality of numerical values, a card display for displaying a card showing a command included in the command information set or symbols related with the numerical values, and a command input acceptance unit to accept an input which selects the card displayed as well as one of the numerical values or symbols attached to the card.