Patents Represented by Attorney Miles & Stockbridge P.C.
  • Patent number: 8232629
    Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: July 31, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
  • Patent number: 8233145
    Abstract: A pattern defect inspection apparatus capable of detecting minute defects on a sample with high sensitivity without generating speckle noise in signals is realized. Substantially the same region on a surface of a wafer is detected by using two detectors at mutually different timings. Output signals from the two detectors are summed and averaged to eliminate noise. Since a large number of rays of illumination light are not simultaneously irradiated to the same region on the wafer, a pattern defect inspection apparatus capable of suppressing noise resulting from interference of a large number of rays, eliminating noise owing to other causes and detecting with high sensitivity minute defects on the sample without the occurrence of speckle noise in the signal can be accomplished.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: July 31, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hidetoshi Nishiyama, Kei Shimura, Sachio Uto, Minori Noguchi
  • Patent number: 8227831
    Abstract: A semiconductor device having a junction FET having improved characteristics is provided. The semiconductor device has a junction FET as a main transistor and has a MISFET as a transistor for control. The junction FET has a first gate electrode, a first source electrode, and a first drain electrode. The MISFET has a second gate electrode, a second source electrode, and a second drain electrode. The MISFET is an n-channel type MISFET and has electric characteristics of an enhancement mode MISFET. The second gate electrode and the second drain electrode of the MISFET are connected to each other by short-circuiting. The first gate electrode of the junction FET and the second source electrode of the MISFET are connected to each other by short-circuiting.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: July 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hidekatsu Onose
  • Patent number: 8227265
    Abstract: A method of measuring a pattern shape of performing a shape measurement of a semiconductor pattern at a high accuracy even when a process margin is narrow with respect to miniaturization of a semiconductor device is provided. In the method of measuring a pattern shape, when a best-match calculated waveform cannot be selected, at least one parameter among shape parameters is set as a fixed value based on information obtained by another measurement apparatus that uses a measurement method independent to the pattern shape measurement, a matching of a library and a detected waveform is performed again, a best-match calculated waveform is selected, and shape information of an object pattern is obtained from the best-match calculated waveform.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: July 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kana Nemoto, Shunichi Matsumoto, Yasuhiro Yoshitake
  • Patent number: 8222651
    Abstract: A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.
    Type: Grant
    Filed: May 8, 2010
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takamitsu Kanazawa, Toshiyuki Hata
  • Patent number: 8223838
    Abstract: The present invention provides a functional block that executes video coding and video decoding based on H.264/AVC. The functional block includes two moving picture processing units, and a memory unit that stores therein data related to the results of processing of first plural macroblocks arranged within one row of one picture by the first moving picture processing unit. Data related to the results of processing of plural adjacent macroblocks, which are selected from the data stored in the memory unit, are transferred to the second moving picture processing unit. The second moving picture processing unit performs processing of one macroblock of second plural macroblocks arranged in the following row, using the transferred data.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenichi Iwata, Seiji Mochizuki, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Yukifumi Kobayashi, Hiroaki Nakata, Koji Hosogi, Masakazu Ehama, Takafumi Yuasa
  • Patent number: 8223328
    Abstract: A surface inspecting apparatus includes an illumination optical system irradiating linearly polarized light to a wafer surface under a plurality of inspection conditions; an imaging optical system capturing an image of the wafer formed by polarization components having an oscillation direction different from that of the linearly polarized light as part of reflected light from the wafer surface irradiated by the linearly polarized light under the plurality of inspection conditions; and an image-processing apparatus for extracting for individual pixels an image having the smallest signal intensity from among images of the wafer captured under the plurality of inspection conditions by the imaging optical system, and for inspecting for the presence of defects in a repeated pattern of the wafer based on an inspection image of the wafer generated by connecting each of the extracted pixels.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 17, 2012
    Assignee: Nikon Corporation
    Inventor: Kazuhiko Fukazawa
  • Patent number: 8221002
    Abstract: A bearing apparatus includes an outer ring (11), an inner ring (12), rolling elements (13) disposed between the two rings, and a seal (15) attached to one of the outer ring and the inner ring and extending toward the other ring. A temperature sensor is fitted to the seal, and hence a temperature of the seal contacting with a rotary wheel can be directly measured. Accordingly, if the temperature measured by the temperature sensor rapidly rises, this implies that some inconvenience might occur, and necessary countermeasures such as immediately stopping an apparatus using the bearing apparatus can be taken before the explicit inconvenience occurs.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: July 17, 2012
    Assignee: NSK Ltd.
    Inventors: Toshiaki Oguchi, Keisuke Yokoyama
  • Patent number: 8222050
    Abstract: In a chip pick-up process after dicing in an assembly process during manufacture of a semiconductor integrated circuit device it is an important subject to diminish a pick-up defect caused by the reduction in thickness of each chip which is proceeding in quick tempo. Particularly, bending of the chip peripheral portion caused by a peeling operation is very likely to induce cracking and chipping of the chip. In the present invention, to solve these problems, in case of peeling a chip from a dicing tape (adhesive tape) or the like while vacuum-chucking the chip by a chucking collet, the flow rate of a vacuum chucking system in the chucking collet is monitored to check a bent state of the chip before complete separation of the first chip from the adhesive tape.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Tsuyoshi Yokomori, Tatsuyuki Okubo
  • Patent number: 8220380
    Abstract: The invention relates to a hydraulic group comprising a reservoir (28) for oil, in which a multiple piston pump (60) is arranged. The individual pumps (61) are cyclically driven by an eccentric ring (29). In order to ensure a permanent immersion of the individual pumps in the reservoir (28), an auxiliary reservoir (47) providing oil for refilling the reservoir (28) is arranged above the reservoir. The auxiliary reservoir (47) is connected to an additional tank (45) by means of a connection line (48).
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: July 17, 2012
    Assignee: Wagner Vermögensverwaltungs-GmbH & Co. KG
    Inventors: Günter Andres, Ulf Sittig, Bernd Thelen, Paul-Heinz Wagner
  • Patent number: 8223563
    Abstract: For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kenji Kozakai, Takeshi Nakamura, Tatsuya Ishii, Motoyasu Tsunoda, Shinya Iguchi, Junichi Maruyama
  • Patent number: 8222082
    Abstract: A technique is provided which allows a chip mounted by wire bonding and a chip mounted by bump electrodes to share a manufacturing process. Both in a case where a chip is electrically coupled to an external circuit by bump electrodes and a case where the chip is electrically coupled to the external circuit by bonding wires, a bump coupling part and a bonding pad are both provided in a single uppermost wiring layer. When the bump electrodes are used, an opening is provided in an insulating film on the bump coupling part and a surface of the bonding pad is covered with the insulating film. On the other hand, when the bonding wires are used, an opening is provided in an insulating film on the bonding pad and a surface of the bump coupling part is covered with the insulating film.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Niichi Ito, Tetsuji Nakamura, Takamitsu Nagaosa, Hisashi Okamura
  • Patent number: 8222712
    Abstract: To achieve a further reduction in the size of a finished product by reducing the number of externally embedded parts, the embedding of a Schottky barrier diode which is relatively large in the amount of current in a semiconductor integrated circuit device has been pursued. In such a case, it is general practice to densely arrange a large number of contact electrodes in a matrix over a Schottky junction region. It has been widely performed to perform a sputter etching process with respect to the surface of a silicide layer at the bottom of each contact hole before a barrier metal layer is deposited. However, in a structure in which electrodes are thus arranged over a Schottky junction region, a reverse leakage current in a Schottky barrier diode is varied by variations in the amount of sputter etching. The present invention is a semiconductor integrated circuit device having a Schottky barrier diode in which contact electrodes are arranged over a guard ring in contact with a peripheral isolation region.
    Type: Grant
    Filed: March 8, 2009
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kunihiko Kato, Shigeya Toyokawa, Kozo Watanabe, Masatoshi Taya
  • Patent number: 8220441
    Abstract: A fuel state control unit for use with internal combustion engines can include a primary heating chamber, a secondary heating chamber, and an expansion chamber. The primary heating chamber has a fuel conduit through which fuel is conveyed. A heater in the primary heating chamber transmits heat to the conveyed fuel in the primary heating chamber. The heater is controlled to maintain a predetermined temperature of the fuel. The heated fuel from the conduit is conveyed into a secondary heating chamber. A pressure plate separates the secondary heating chamber from the expansion chamber. The ports of the pressure plate can regulate the flow of the fuel into the expansion chamber. The heated fuel in the expansion chamber can then be conveyed to an engine so as to increase engine efficiency and reduce the amount of pollutant gases in the engine exhaust.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: July 17, 2012
    Assignee: Nox Free Solutions LLC
    Inventors: John David Webb, Robert Ralph Webb, Jr., Michael Eugene Clason, Joe Humbert
  • Patent number: 8221001
    Abstract: A bearing apparatus includes a rolling bearing (16) having an outer ring (16a), an inner ring (16b), and rolling elements (16c) disposed between the inner ring (16b) and the outer ring (16a), a temperature sensor (TS) for measuring an internal temperature of the rolling bearing and a lubrication unit (22). The lubrication unit supplies lubricating oil in a quantity corresponding to the temperature detected by the temperature sensor, to the rolling bearing. With this configuration, it is feasible to provide the bearing apparatus capable of ensuring a sufficiently long life under the condition of high-speed rotations. The bearing apparatus is suitable for use in a spindle for a machine tool.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: July 17, 2012
    Assignee: NSK Ltd.
    Inventors: Koichi Morita, Keisuke Yokoyama
  • Patent number: 8222720
    Abstract: There are constituted by a tab (1b) on which a semiconductor chip (2) is mounted, a sealing portion (3) formed by resin-sealing the semiconductor chip (2), a plurality of leads (1a) each having a mounted surface (1d) exposed to a peripheral portion of a rear surface (3a) of the sealing portion (3) and a sealing-portion forming surface (1g) disposed on an opposite side thereto, and a wire (4) for connecting a pad (2a) of the semiconductor chip (2) and a lead (1a), wherein the length (M) between inner ends (1h) of the sealing-portion forming surfaces (1g) of the leads (1a) disposed so as to oppose to each other is formed to be larger than the length (L) between inner ends (1h) of the mounted surfaces (1d). Thereby, a chip mounting region surrounded by the inner end (1h) of the sealing-portion forming surface (1g) of each lead (1a) can be expanded and the size of the mountable chip is increased.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: July 17, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshihiko Shimanuki, Yoshihiro Suzuki, Koji Tsuchiya
  • Patent number: 8221201
    Abstract: A ventilation device for ventilation of a building having a double-window construction with an air space. The device communicates with the open air space and has four throttles. The first and the second throttles can selectively cut off the passage of air from the air space into a first and a second chamber, respectively, of the device. The third throttle can selectively cut off the passage of air from the first chamber and into the building. The fourth throttle can selectively cut off the passage of air between the open air space and the first and the second chamber. Temperature-sensitive actuators can activate the throttles, selectively adjusting air flow.
    Type: Grant
    Filed: October 19, 2005
    Date of Patent: July 17, 2012
    Inventors: Poul Christensen, Jens Arboe Harild, Soren Møller Madsen, Niels Herskind
  • Patent number: D664511
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 31, 2012
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Kouhei Taniguchi, Takayuki Matsuzaki, Shinya Katou, Kouji Komorida, Michio Mashino, Tatsuya Sakuta, Rie Katou
  • Patent number: D664512
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: July 31, 2012
    Assignee: Hitachi Chemical Comapany, Ltd.
    Inventors: Kouhei Taniguchi, Takayuki Matsuzaki, Shinya Katou, Kouji Komorida, Michio Mashino, Tatsuya Sakuta, Rie Katou
  • Patent number: D664662
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: July 31, 2012
    Assignee: VITA Zahnfabrik H. Rauter GmbH & Co. KG
    Inventor: Wolfgang Meyer-Hayoz